Re: [PATCH 1/1] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

[LIU Zhiwei]

On 2024/5/17 1:10, Daniel Henrique Barboza wrote:

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

Cc: Akihiko Odaki <akihiko.od...@daynix.com>
Cc: Alex Bennée <alex.ben...@linaro.org>
Reported-by: Robin Dapp <rdapp....@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>

Reviewed-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>

Zhiwei

---
  target/riscv/gdbstub.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index d0cc5762c2..358158c42a 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -288,7 +288,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState 
*cs, int base_reg)
  static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int 
base_reg)
  {
      RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int reg_width = cpu->cfg.vlenb << 3;
      GDBFeatureBuilder builder;
      int i;