Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-a64.h| 4 +
target/arm/tcg/translate.h | 5 +
target/arm/tcg/a64.decode | 27 +
target/arm/tcg/translate-a64.c | 205 +
target/arm/tcg/vec_helper.c| 4 +
5 files changed, 143 insertions(+), 102 deletions(-)
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
index b79751a717..371388f61b 100644
--- a/target/arm/tcg/helper-a64.h
+++ b/target/arm/tcg/helper-a64.h
@@ -133,6 +133,10 @@ DEF_HELPER_4(cpyfp, void, env, i32, i32, i32)
DEF_HELPER_4(cpyfm, void, env, i32, i32, i32)
DEF_HELPER_4(cpyfe, void, env, i32, i32, i32)
+DEF_HELPER_FLAGS_5(gvec_fdiv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_5(gvec_fmulx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
i32)
DEF_HELPER_FLAGS_5(gvec_fmulx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
i32)
DEF_HELPER_FLAGS_5(gvec_fmulx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
i32)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 80e85096a8..ecfa242eef 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -252,6 +252,11 @@ static inline int shl_12(DisasContext *s, int x)
return x << 12;
}
+static inline int xor_2(DisasContext *s, int x)
+{
+return x ^ 2;
+}
+
static inline int neon_3same_fp_size(DisasContext *s, int x)
{
/* Convert 0==fp32, 1==fp16 into a MO_* value */
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index e28f58bd9a..828ea2d62a 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -21,6 +21,7 @@
%rd 0:5
%esz_sd 22:1 !function=plus_2
+%esz_hsd22:2 !function=xor_2
%hl 11:1 21:1
%hlm11:1 20:2
@@ -37,6 +38,7 @@
@rrr_h ... rm:5 .. rn:5 rd:5 _e esz=1
@rrr_sd ... rm:5 .. rn:5 rd:5 _e esz=%esz_sd
+@rrr_hsd ... rm:5 .. rn:5 rd:5 _e esz=%esz_hsd
@rrx_h .. .. rm:4 . . rn:5 rd:5 _e esz=1 idx=%hlm
@rrx_s .. . rm:5 . . rn:5 rd:5 _e esz=2 idx=%hl
@@ -697,22 +699,47 @@ INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5
### Advanced SIMD scalar three same
+FADD_s 0001 1110 ..1 . 0010 10 . . @rrr_hsd
+FSUB_s 0001 1110 ..1 . 0011 10 . . @rrr_hsd
+FDIV_s 0001 1110 ..1 . 0001 10 . . @rrr_hsd
+FMUL_s 0001 1110 ..1 . 10 . . @rrr_hsd
+
FMULX_s 0101 1110 010 . 00011 1 . . @rrr_h
FMULX_s 0101 1110 0.1 . 11011 1 . . @rrr_sd
### Advanced SIMD three same
+FADD_v 0.00 1110 010 . 00010 1 . . @qrrr_h
+FADD_v 0.00 1110 0.1 . 11010 1 . . @qrrr_sd
+
+FSUB_v 0.00 1110 110 . 00010 1 . . @qrrr_h
+FSUB_v 0.00 1110 1.1 . 11010 1 . . @qrrr_sd
+
+FDIV_v 0.10 1110 010 . 00111 1 . . @qrrr_h
+FDIV_v 0.10 1110 0.1 . 1 1 . . @qrrr_sd
+
+FMUL_v 0.10 1110 010 . 00011 1 . . @qrrr_h
+FMUL_v 0.10 1110 0.1 . 11011 1 . . @qrrr_sd
+
FMULX_v 0.00 0111 010 . 00011 1 . . @qrrr_h
FMULX_v 0.00 1110 0.1 . 11011 1 . . @qrrr_sd
### Advanced SIMD scalar x indexed element
+FMUL_si 0101 00 .. 1001 . 0 . . @rrx_h
+FMUL_si 0101 10 . . 1001 . 0 . . @rrx_s
+FMUL_si 0101 11 0 . 1001 . 0 . . @rrx_d
+
FMULX_si0111 00 .. 1001 . 0 . . @rrx_h
FMULX_si0111 10 . . 1001 . 0 . . @rrx_s
FMULX_si0111 11 0 . 1001 . 0 . . @rrx_d
### Advanced SIMD vector x indexed element
+FMUL_vi 0.00 00 .. 1001 . 0 . . @qrrx_h
+FMUL_vi 0.00 10 . . 1001 . 0 . . @qrrx_s
+FMUL_vi 0.00 11 0 . 1001 . 0 . . @qrrx_d
+
FMULX_vi0.10 00 .. 1001 . 0 . . @qrrx_h
FMULX_vi0.10 10 . . 1001 . 0 . . @qrrx_s
FMULX_vi0.10 11 0 . 1001 . 0 . . @qrrx_d
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 33da0c5f0f..f3b037a7c6 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -4888,6 +4888,34 @@ static bool do_fp3_scalar(DisasContext *s, arg_rrr_e *a,
const FPScalar *f)
return true;
}
+static const FPScalar f_scalar_fadd = {
+gen_helper_vfp_addh,
+gen_helper_vfp_adds,
+gen_helper_vfp_addd,
+};
+TRANS(FADD_s, do_fp3_scalar, a, _scalar_fadd)
+
+static const FPScalar
