[Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt

commands, in TCG mode : invalid bits: 0200 for opcode: 1f - 16 - 08 (7e09322c) 3fff799feca0 This patch adds the extended opcodes as no-ops just like the 'dcbt' instruction. Other 'dcb*' instructions might be impacted but they have not showed up yet. Signed-off-by: Cédric Le Goater c

[Qemu-devel] [PATCH v2] target-ppc: add extended opcodes for dcbt/dcbtst

commands, in TCG mode : invalid bits: 0200 for opcode: 1f - 16 - 08 (7e09322c) 3fff799feca0 This patch adds the extended opcodes for dcbt/dcbtst as no-ops just like the 'dcbt' instruction. Signed-off-by: Cédric Le Goater c...@fr.ibm.com --- Changes in v2: - added extended

[Qemu-devel] [RFC PATCH 0/2] vhost: support for cross endian

These two small patches add a VHOST_VRING_F_BYTESWAP flag to the vring which will be used by the kernel to byteswap the different vring indexes. The kernel patchset can be found on the kvm@ and kvm-ppc@ mailing lists. Cédric Le Goater (2): vhost: add VHOST_VRING_F_BYTESWAP flag vhost_net

[Qemu-devel] [RFC PATCH 1/2] vhost: add VHOST_VRING_F_BYTESWAP flag

When the guest and the host have a different endian order, the data being accessed in the vring queues needs to be byteswapped. This patch adds a VHOST_VRING_F_BYTESWAP flag to inform the vhost kernel backend to byteswap vring data. Signed-off-by: Cédric Le Goater c...@fr.ibm.com --- hw

[Qemu-devel] [RFC PATCH 2/2] vhost_net: re-enable when cross endian

revert 371df9f5e0f1 vhost-net: disable when cross-endian Signed-off-by: Cédric Le Goater c...@fr.ibm.com --- hw/net/vhost_net.c | 19 --- 1 file changed, 19 deletions(-) diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c index 4e3a06162291..721fb2da52f8 100644 --- a/hw/net

[Qemu-devel] [PATCH] target-ppc: explicitly save page table headers in big endian

routine to write explicitly the kvm_get_htab_header structs in big endian. The ptes are left untouched. Signed-off-by: Cédric Le Goater c...@fr.ibm.com Cc: Paul Mackerras pau...@samba.org Cc: Alexey Kardashevskiy a...@ozlabs.ru Cc: Gregory Kurz gk...@linux.vnet.ibm.com --- This patch needs

Re: [Qemu-devel] [PATCH v4 00/17] Add an IPMI device to QEMU

On 11/12/2015 08:02 PM, miny...@acm.org wrote: > This is a long delayed patch set, but I think I have things reworked > to make Igor happy with the way ACPI and SMBIOS work. This is more > consistent with the way most other things work, anyway. It did > require adding stubs for systems without

Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/77] ppc: Add "native" POWER8 platform

On 11/30/2015 09:09 PM, Benjamin Herrenschmidt wrote: > On Mon, 2015-11-30 at 19:15 +0100, Cédric Le Goater wrote: >> The pnor file is compiled from github. The patch is below (without the dirty >> cut and paste I did in loader.c). The offset for the PAYLOAD and BOOTKERNEL >>

Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/77] ppc: Add "native" POWER8 platform

On 12/07/2015 02:25 AM, Stewart Smith wrote: > Cédric Le Goater <c...@fr.ibm.com> writes: >> On 11/28/2015 08:59 AM, Benjamin Herrenschmidt wrote: >>> On Fri, 2015-11-27 at 11:21 +0100, Alexander Graf wrote: >>>> >>>> How does real hardwar

[Qemu-devel] [PATCH 2/8] ipmi: add get and set SENSOR_TYPE commands

Signed-off-by: Cédric Le Goater <c...@fr.ibm.com> --- hw/ipmi/ipmi_bmc_sim.c | 51 -- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c index 559e1398d669..061db8437479 100644 --

[Qemu-devel] [PATCH 1/8] ipmi: fix SDR length value

The IPMI BMC simulator populates the SDR table with a set of initial SDRs. The length of each SDR is taken from the record itself (byte 4) which does not include the size of the header. But, the full length (header + data) is required by the sdr_add_entry() routine. Signed-off-by: Cédric Le

[Qemu-devel] [PATCH 7/8] ipmi: introduce an ipmi_bmc_init_sensor() API

->rec_length + 5, >sensor_owner_number); Signed-off-by: Cédric Le Goater <c...@fr.ibm.com> --- hw/ipmi/ipmi_bmc_sim.c | 61 +- include/hw/ipmi/ipmi.h | 37 ++ 2 files changed, 87 insertions(+), 11 deletions(-)

[Qemu-devel] [PATCH 3/8] ipmi: add GET_SYS_RESTART_CAUSE chassis command

This is a simulator. Just return an unknown cause (0). Signed-off-by: Cédric Le Goater <c...@fr.ibm.com> --- hw/ipmi/ipmi_bmc_sim.c | 20 ++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c index 061db8

[Qemu-devel] [PATCH 6/8] ipmi: add SET_SENSOR_READING command (tentative try)

"Boot Count" sensor. Signed-off-by: Cédric Le Goater <c...@fr.ibm.com> --- hw/ipmi/ipmi_bmc_sim.c | 141 - 1 file changed, 140 insertions(+), 1 deletion(-) diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c index c3a06d0ac7e

[Qemu-devel] [PATCH 8/8] ipmi: introduce an ipmi_bmc_gen_event() API

It will be used to fill the message buffer with custom events expected by some systems. Typically, an Open PowerNV platform guest is notified with an OEM SEL message before a shutdown or a reboot. Signed-off-by: Cédric Le Goater <c...@fr.ibm.com> --- hw/ipmi/ipmi_bmc_sim.

[Qemu-devel] [PATCH 5/8] ipmi: add ACPI power and GUID commands

Signed-off-by: Cédric Le Goater <c...@fr.ibm.com> --- hw/ipmi/ipmi_bmc_sim.c | 55 ++ 1 file changed, 55 insertions(+) diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c index 60586a67104e..c3a06d0ac7e4 100644 --- a/hw/ipmi/ipmi_bmc

[Qemu-devel] [PATCH 4/8] ipmi: add FRU support

This patch provides a simplistic FRU support for the IPMI BMC simulator. The FRU area contains 32 entries * 256 bytes which should be enough to start some simulation. Signed-off-by: Cédric Le Goater <c...@fr.ibm.com> --- hw/ipmi/ipmi_bmc_sim.c

[Qemu-devel] [PATCH 0/8] ipmi: a couple of enhancements to the BMC simulator

/legoater/qemu/commits/ipmi Thanks, Cédric Le Goater (8): ipmi: fix SDR length value ipmi: add get and set SENSOR_TYPE commands ipmi: add GET_SYS_RESTART_CAUSE chassis command ipmi: add FRU support ipmi: add ACPI power and GUID commands ipmi: add SET_SENSOR_READING command (tentative try

Re: [Qemu-devel] [PATCH 2/8] ipmi: add get and set SENSOR_TYPE commands

On 01/06/2016 10:55 AM, Greg Kurz wrote: > On Tue, 5 Jan 2016 18:29:56 +0100 > Cédric Le Goater <c...@fr.ibm.com> wrote: > >> Signed-off-by: Cédric Le Goater <c...@fr.ibm.com> >> --- > > Acked-by: Greg Kurz <gk...@linux.vnet.ibm.com> > > Just

Re: [Qemu-devel] [PATCH 1/8] ipmi: fix SDR length value

On 01/05/2016 08:59 PM, Eric Blake wrote: > On 01/05/2016 10:29 AM, Cédric Le Goater wrote: > > [meta-comment] Your messages were not marked in-reply-to: the 0/8 cover > letter, but came through as separate threads. This makes it harder to > follow, especially in mail clients that

Re: [Qemu-devel] [PATCH 06/12] 4byte address mode support added.

Hello Marcin, On 12/16/2015 01:57 PM, marcin.krzemin...@nokia.com wrote: > From: Marcin Krzeminski > > Signed-off-by: Marcin Krzeminski > --- > hw/block/m25p80.c | 31 --- > 1 file changed, 28

Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/77] ppc: Add "native" POWER8 platform

On 11/28/2015 08:59 AM, Benjamin Herrenschmidt wrote: > On Fri, 2015-11-27 at 11:21 +0100, Alexander Graf wrote: >> >> How does real hardware store petitboot? If it's flash, you could pass it >> in using -pflash and thus model things even more closely and allow users >> to just take the ROM image

Re: [Qemu-devel] [PATCH v4 03/17] ipmi: Add a local BMC simulation

On 11/24/2015 08:46 PM, Corey Minyard wrote: > On 11/24/2015 07:31 AM, Cédric Le Goater wrote: >> A few comments below, > > Thanks a bunch for the review. As you probably have guessed, this was > not really intended as a fully functional BMC, though it has most of the >

Re: [Qemu-devel] [PATCH v4 03/17] ipmi: Add a local BMC simulation

A few comments below, On 11/12/2015 08:02 PM, miny...@acm.org wrote: > From: Corey Minyard > > This provides a minimal local BMC, basically enough to comply with the > spec and provide a complete watchdog timer (including a sensor, SDR, > and event). > > Signed-off-by:

Re: [Qemu-devel] [PATCH 2/8] ipmi: add get and set SENSOR_TYPE commands

On 01/08/2016 09:23 PM, Corey Minyard wrote: > Acked-by: Corey Minyard <cminy...@mvista.com> > > I agree with Greg's comments, too. Me also. I will rework the code to use ARRAY_SIZE or something similar. Thanks, C. > -corey > > On 01/05/2016 11:29 AM, Cédric Le Goa

Re: [Qemu-devel] [PATCH 4/8] ipmi: add FRU support

Hello, On 01/08/2016 08:41 PM, Corey Minyard wrote: > On 01/05/2016 11:29 AM, Cédric Le Goater wrote: >> This patch provides a simplistic FRU support for the IPMI BMC >> simulator. The FRU area contains 32 entries * 256 bytes which should >> be enough to start some simulat

Re: [Qemu-devel] [PATCH 1/8] ipmi: fix SDR length value

On 01/08/2016 09:20 PM, Corey Minyard wrote: > On 01/06/2016 02:14 AM, Cédric Le Goater wrote: >> On 01/05/2016 08:59 PM, Eric Blake wrote: >>> On 01/05/2016 10:29 AM, Cédric Le Goater wrote: >>> >>> [meta-comment] Your messages were not marked in-reply-to

Re: [Qemu-devel] [PATCH 5/8] ipmi: add ACPI power and GUID commands

On 01/08/2016 08:46 PM, Corey Minyard wrote: > On 01/05/2016 11:29 AM, Cédric Le Goater wrote: >> Signed-off-by: Cédric Le Goater <c...@fr.ibm.com> >> --- >> hw/ipmi/ipmi_bmc_sim.c | 55 >> ++ >> 1 file cha

Re: [Qemu-devel] [PATCH 7/8] ipmi: introduce an ipmi_bmc_init_sensor() API

, but if you > need something more extensive we probably should think about something > else. > > A few comments inline, too. > > On 01/05/2016 11:30 AM, Cédric Le Goater wrote: >> This routine will let qemu platforms populate the sdr/sensor tables of >> the IPMI

Re: [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode

On 06/03/2016 05:47 PM, Mark Cave-Ayland wrote: > On 03/06/16 15:14, Mark Cave-Ayland wrote: > >> On 03/06/16 15:06, Cedric Le Goater wrote: >> >>> On 06/03/2016 04:00 PM, Cédric Le Goater wrote: >>>> Hello Mark, >>>> >>>> On 06/03

Re: [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode

Hello Mark, On 06/03/2016 03:52 PM, Mark Cave-Ayland wrote: > On 03/06/16 13:11, Cédric Le Goater wrote: > >> This is follow up to complete the serie "ppc: preparing pnv landing >> (round 2)" plus a little fix on instruction privileges. >> >> Test

Re: [Qemu-devel] [PATCH] hw/timer: Add value matching support to aspeed_timer

h let us boot directly for the OpenBMC flash images. Acked-by: Cédric Le Goater <c...@kaod.org> Thanks C. >> --- >> >> The change pulls out ptimer in favour of the regular timer infrastructure. >> As a >> consequence it implements the conversions between ticks and ti

Re: [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode

On 06/06/2016 08:38 AM, Mark Cave-Ayland wrote: > On 06/06/16 07:30, Cedric Le Goater wrote: > >> On 06/06/2016 08:27 AM, Cédric Le Goater wrote: >>> On 06/06/2016 12:26 AM, Mark Cave-Ayland wrote: >>>> On 05/06/16 18:41, Cédric Le Goater wrote: >>>> &

Re: [Qemu-devel] [RFC/PATCH] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode

On 06/06/2016 12:23 PM, Benjamin Herrenschmidt wrote: > This ports the existing 64-bit mechanism to 32-bit, thus series > of 64 tlbie's followed by a sync like some versions of Darwin > (ab)use will result in a single flush. > > We apply a pending flush on any sync instruction though, as Darwin >

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] ppc: complete the new HV mode

On 06/06/2016 06:17 AM, Benjamin Herrenschmidt wrote: > On Sun, 2016-06-05 at 19:41 +0200, Cédric Le Goater wrote: >> >> Here is a fix I think. Could you give it a try ? > > This is somewhat wrong... > >> commit cd0c6f473532 ('ppc: Do some batching of T

Re: [Qemu-devel] [PATCH 2/2] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors

blow the whole tlb when tlbie > is executed. > > Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> Looks good on G3 and G4 running macosx10.2 and macosx10.4. Tested-by: Cédric Le Goater <c...@kaod.org> > --- > target-ppc/mmu_helper.c | 8 >

Re: [Qemu-devel] [PATCH 1/2] ppc: Properly tag the translation cache based on MMU mode

igned-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> Looks good on G3 and G4 running macosx10.2 and macosx10.4. Tested-by: Cédric Le Goater <c...@kaod.org> > --- > target-ppc/helper_regs.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/t

Re: [Qemu-devel] [PATCH v3 10/10] ipmi: provide support for FRUs

On 03/15/2016 03:30 PM, Michael S. Tsirkin wrote: > On Thu, Mar 10, 2016 at 03:04:03PM +0100, Cédric Le Goater wrote: >> This patch provides a simple FRU support for the BMC simulator. FRUs >> are loaded from a file which name is specified in the object >> properties, each

Re: [Qemu-devel] [PATCH v2] i2c: add aspeed i2c controller

On 06/06/2016 05:05 PM, Peter Maydell wrote: > On 31 May 2016 at 15:18, Cédric Le Goater <c...@kaod.org> wrote: >> The Aspeed AST2400 integrates a set of 14 I2C/SMBus bus controllers >> directly connected to the APB bus. They can be programmed as master or >> slave b

[Qemu-devel] [PATCH 00/10] rework exception model to support the HV mode

Hello, Here is a new set bringing more changes required for the powernv platform. The major one is the rework of the exception model to support the HV mode. It was tested with a pseries guest, KVM and TCG, and with a mac99 guest ! The next serie will cover a rework of XICS to support native

[Qemu-devel] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

From: Benjamin Herrenschmidt This reworks emulation of the various "rfi" variants. I removed some masking bits that I couldn't make sense of, the only bit that I am aware we should mask here is POW, the CPU's MSR mask should take care of the rest. This also fixes some

[Qemu-devel] [PATCH 02/10] ppc: Create cpu_ppc_set_papr() helper (for LPCR)

Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> Reviewed-by: David Gibson <da...@gibson.dropbear.id.au> [clg: previous commit 26a7f1291bb5 did not include the LPCR setting as it was not needed at the time ] Signed-off-by: Cédric Le Goater <c...@kaod

[Qemu-devel] [PATCH 05/10] ppc: Fix generation if ISI/DSI vs. HV mode

From: Benjamin Herrenschmidt Under some circumstances, we need to direct ISI and DSI interrupts at the hypervisor, turning them into HISI/HDSI, and using different SPRs (HDSISR and HDAR) depending on the combination of MSR_DR and the corresponding VPM bits in LPCR.

[Qemu-devel] [PATCH 06/10] ppc: Rework generation of priv and inval interrupts

chmidt <b...@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <c...@kaod.org> --- linux-user/main.c| 1 + target-ppc/excp_helper.c | 19 ++ target-ppc/translate.c | 690 --- 3 files chang

[Qemu-devel] [PATCH 03/10] ppc: Rework POWER7 & POWER8 exception model (part 2)

From: Benjamin Herrenschmidt <b...@kernel.crashing.org> Properly implement LPES0/1 handling for HV vs. !HV mode. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> [clg: AIL implementation was fixed in commit 5c94b2a5e5ef fixed checkpatch.pl errors ] Signed-off-b

[Qemu-devel] [PATCH 07/10] ppc: Add real mode CI load/store instructions for P7 and P8

] Signed-off-by: Cédric Le Goater <c...@kaod.org> --- This patch still has a couple of checkpatch issues which I did not know quite understand: ERROR: Macros with complex values should be enclosed in parenthesis #176: FILE: target-ppc/translate.c:10238: +#define GEN_LDX_E(name, ldop, opc2, opc3

[Qemu-devel] [PATCH 04/10] ppc: Fix POWER7 and POWER8 exception definitions

From: Benjamin Herrenschmidt <b...@kernel.crashing.org> We were initializing unused ones and missing some Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> Reviewed-by: David Gibson <da...@gibson.dropbear.id.au> [clg: fixed checkpatch.pl errors ] Signed-off-by: C

[Qemu-devel] [PATCH 08/10] ppc: Turn a bunch of booleans from int to bool

From: Benjamin Herrenschmidt Signed-off-by: Benjamin Herrenschmidt Reviewed-by: David Gibson --- target-ppc/translate.c | 37 ++--- 1 file changed, 18 insertions(+), 19

[Qemu-devel] [PATCH 09/10] ppc: Move exception generation code out of line

From: Benjamin Herrenschmidt There's no point inlining this, if you hit the exception case you exit anyway, and not inlining saves about 100K of code size (and cache footprint). Signed-off-by: Benjamin Herrenschmidt ---

[Qemu-devel] [PATCH 10/10] ppc: Add P7/P8 Power Management instructions

ch.pl errors ] Signed-off-by: Cédric Le Goater <c...@kaod.org> --- target-ppc/cpu-qom.h| 9 + target-ppc/cpu.h| 17 - target-ppc/excp_helper.c| 59 + target-ppc/helper.h | 1 + target-ppc/tra

[Qemu-devel] [PATCH 2/3] ppc: Better figure out if processor has HV mode

ned also when PR=1 and conditions are fixed accordingly. stripped unwanted tabs.] Signed-off-by: Cédric Le Goater <c...@kaod.org> --- target-ppc/cpu.h| 4 target-ppc/translate.c | 4 +++- target-ppc/translate_init.c | 19 +++ 3 files chan

[Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode

figure out if processor has HV mode Cédric Le Goater (1): ppc: fix hrfid, tlbia and slbia privilege target-ppc/cpu.h| 4 target-ppc/excp_helper.c| 8 ++-- target-ppc/helper_regs.h| 4 ++-- target-ppc/translate.c | 10 ++ target-ppc/translate_i

[Qemu-devel] [PATCH 1/3] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV

From: Benjamin Herrenschmidt This helper is only used by the various instructions that can alter MSR and not interrupts. Add a comment to that effect to the interrupt code as well in case somebody wants to change this Signed-off-by: Benjamin Herrenschmidt

[Qemu-devel] [PATCH 3/3] ppc: fix hrfid, tlbia and slbia privilege

commit 74693da98894 ('ppc: tlbie, tlbia and tlbisync are HV only') introduced some extra checks on the instruction privilege. slbia was changed wrongly and hrfid, tlbia were forgotten. Signed-off-by: Cédric Le Goater <c...@kaod.org> --- target-ppc/translate.c | 6 +++--- 1 file chan

Re: [Qemu-devel] [Qemu-ppc] [PATCH 07/12] ppc: Better figure out if processor has HV mode

On 05/28/2016 11:52 AM, David Gibson wrote: > On Fri, May 27, 2016 at 09:56:32AM +0200, Cédric Le Goater wrote: >> On 05/27/2016 05:38 AM, David Gibson wrote: >>> On Tue, May 03, 2016 at 06:03:29PM +0200, Cédric Le Goater wrote: >>>> From: Benjamin Herrensch

Re: [Qemu-devel] [PATCH 09/10] ppc: Move exception generation code out of line

On 06/13/2016 09:44 AM, Thomas Huth wrote: > On 13.06.2016 07:24, Cédric Le Goater wrote: >> From: Benjamin Herrenschmidt <b...@kernel.crashing.org> >> >> There's no point inlining this, if you hit the exception case you exit >> anyway, and not inlining saves a

Re: [Qemu-devel] [PATCH] m25p80: fix test on blk_pread() return value

On 06/13/2016 06:47 PM, Eric Blake wrote: > On 06/13/2016 10:25 AM, Cédric Le Goater wrote: > >> >> It seems that commit 243e6f69c129 ("m25p80: Switch to byte-based block >> access") >> is bringing another issue : >> >> qemu-system-arm: &

Re: [Qemu-devel] [PATCH] m25p80: fix test on blk_pread() return value

in m25p80.c, now writes with a len of 0x100, which the page size in flash modules. commit 243e6f69c129 ("m25p80: Switch to byte-based block access") removed the alignment on BDRV_SECTOR_SIZE. So I think the safest is to restore the alignment on writes. see below. If this is ok, I will send a

Re: [Qemu-devel] [PATCH 05/10] ppc: Fix generation if ISI/DSI vs. HV mode

On 06/14/2016 08:34 AM, David Gibson wrote: > On Mon, Jun 13, 2016 at 07:24:51AM +0200, Cédric Le Goater wrote: >> From: Benjamin Herrenschmidt <b...@kernel.crashing.org> >> >> Under some circumstances, we need to direct ISI and DSI interrupts >> at the hyperv

Re: [Qemu-devel] [PATCH 02/10] ppc: Create cpu_ppc_set_papr() helper (for LPCR)

On 06/14/2016 08:15 AM, David Gibson wrote: > On Mon, Jun 13, 2016 at 07:24:48AM +0200, Cédric Le Goater wrote: >> From: Benjamin Herrenschmidt <b...@kernel.crashing.org> >> >> And move the code adjusting the MSR mask and calling kvmppc_set_papr() >> to it. This a

Re: [Qemu-devel] [PATCH] m25p80: fix test on blk_pread() return value

On 06/14/2016 10:38 AM, Kevin Wolf wrote: > Am 14.06.2016 um 10:02 hat Cédric Le Goater geschrieben: >>>> #4 0x7fa81c6694ac in bdrv_aligned_pwritev (bs=0x7fa81d4dd050, >>>> req=, offset=30878208, >>>> bytes=512, qiov=0x7fa7f47fee60, flags=0) &g

[Qemu-devel] [PATCH] ssi: change ssi_slave_init to be a realize ops

This enables qemu to handle late inits and report errors. All the SSI slave routine names were changed accordingly. Code was modified to handle errors when possible (m25p80) Tested with the m25p80 slave object. Suggested-by: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Cédric Le Goa

Re: [Qemu-devel] [PATCH 1/9] m25p80: Replace JEDEC ID masking with function.

On 06/15/2016 03:41 PM, marcin.krzemin...@nokia.com wrote: > From: Marcin Krzeminski > > Instead of always reading and comparing jededc ID, > replace it by function. > > Signed-off-by: Marcin Krzeminski Looks good to me. Some minor

Re: [Qemu-devel] [PATCH] m25p80: provide a realize to support late inits.

On 06/15/2016 04:07 PM, Peter Maydell wrote: > On 15 June 2016 at 15:00, Cédric Le Goater <c...@kaod.org> wrote: >> We also need to realize() the SSISlave part of the object. This is why >> the previous realize() ops is stored in M25P80Class and called in the &g

[Qemu-devel] [PATCH v2] m25p80: provide a realize to support late inits.

-by: Cédric Le Goater <c...@kaod.org> --- Should apply on top of : m25p80: fix test on blk_pread() return value https://lists.gnu.org/archive/html/qemu-devel/2016-05/msg05574.html Changes since v2 : - Added a FIXME comment removed in v1 hw/block/m25p80.c

Re: [Qemu-devel] [PATCH] m25p80: fix test on blk_pread() return value

Hello Eric, On 06/13/2016 06:47 PM, Eric Blake wrote: > On 06/13/2016 10:25 AM, Cédric Le Goater wrote: > >> >> It seems that commit 243e6f69c129 ("m25p80: Switch to byte-based block >> access") >> is bringing another issue : >> >> qemu-s

Re: [Qemu-devel] [PATCH] m25p80: fix test on blk_pread() return value

Hello Eric, On 05/31/2016 04:36 PM, Eric Blake wrote: > On 05/31/2016 08:29 AM, Cédric Le Goater wrote: >> On 05/31/2016 04:26 PM, Eric Blake wrote: >>> On 05/31/2016 05:36 AM, Cédric Le Goater wrote: >>>> commit 243e6f69c129 ("m25p80: Switch to byte-based bl

Re: [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode

Hello Mark, On 06/03/2016 03:52 PM, Mark Cave-Ayland wrote: > On 03/06/16 13:11, Cédric Le Goater wrote: > >> This is follow up to complete the serie "ppc: preparing pnv landing >> (round 2)" plus a little fix on instruction privileges. >> >> Test

Re: [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode

On 06/06/2016 12:26 AM, Mark Cave-Ayland wrote: > On 05/06/16 18:41, Cédric Le Goater wrote: > >> Hello Mark, >> >> On 06/03/2016 03:52 PM, Mark Cave-Ayland wrote: >>> On 03/06/16 13:11, Cédric Le Goater wrote: >>> >>>> This is follo

Re: [Qemu-devel] [Qemu-ppc] [PATCH 07/12] ppc: Better figure out if processor has HV mode

On 05/27/2016 06:41 AM, Thomas Huth wrote: > On 27.05.2016 05:38, David Gibson wrote: >> On Tue, May 03, 2016 at 06:03:29PM +0200, Cédric Le Goater wrote: >>> From: Benjamin Herrenschmidt <b...@kernel.crashing.org> >>> >>> We use an env. flag wh

Re: [Qemu-devel] [PATCH] virtio: move bi-endian target support to a single location

io and bi-endian guests. > > Signed-off-by: Greg Kurz <gk...@linux.vnet.ibm.com> biendian-ness being only used by virtio devices, I think this is a good place where to put it. Acked-by: Cédric Le Goater <c...@kaod.org> > --- > hw/virtio/vhost.c

Re: [Qemu-devel] [Qemu-ppc] [PULL 04/12] ppc: tlbie, tlbia and tlbisync are HV only

On 06/02/2016 09:45 AM, Mark Cave-Ayland wrote: > On 02/06/16 08:37, Cédric Le Goater wrote: >> On 06/02/2016 05:17 AM, David Gibson wrote: >>> On Wed, Jun 01, 2016 at 08:03:08AM +0100, Mark Cave-Ayland wrote: >>>> On 01/06/16 03:15, David Gibson wrote: >>&g

Re: [Qemu-devel] [Qemu-ppc] [PULL 04/12] ppc: tlbie, tlbia and tlbisync are HV only

On 06/02/2016 05:17 AM, David Gibson wrote: > On Wed, Jun 01, 2016 at 08:03:08AM +0100, Mark Cave-Ayland wrote: >> On 01/06/16 03:15, David Gibson wrote: >> >>> On Tue, May 31, 2016 at 11:28:49PM +0100, Mark Cave-Ayland wrote: On 31/05/16 01:41, David Gibson wrote: > From: Benjamin

Re: [Qemu-devel] [Qemu-ppc] [PULL 04/12] ppc: tlbie, tlbia and tlbisync are HV only

On 06/02/2016 08:09 PM, Mark Cave-Ayland wrote: > On 02/06/16 09:47, Mark Cave-Ayland wrote: > >> On 02/06/16 09:23, Cédric Le Goater wrote: >> >>> On 06/02/2016 09:45 AM, Mark Cave-Ayland wrote: >>>> On 02/06/16 08:37, Cédric Le Goater wrote: >>&

Re: [Qemu-devel] [Qemu-ppc] [PATCH 07/12] ppc: Better figure out if processor has HV mode

On 05/27/2016 05:38 AM, David Gibson wrote: > On Tue, May 03, 2016 at 06:03:29PM +0200, Cédric Le Goater wrote: >> From: Benjamin Herrenschmidt <b...@kernel.crashing.org> >> >> We use an env. flag which is set to the initial value of MSR_HVB in >> the msr_mas

[Qemu-devel] [PATCH] m25p80: fix test on blk_pread() return value

commit 243e6f69c129 ("m25p80: Switch to byte-based block access") replaced blk_read() calls with blk_pread() but return values are different. Signed-off-by: Cédric Le Goater <c...@kaod.org> --- hw/block/m25p80.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Ind

[Qemu-devel] [PATCH v2] i2c: add aspeed i2c controller

). Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> --- Changes since v1 : - rebased on mainline qemu - added include "qemu/log.h" to fix compile breakage hw/arm/ast2400.c| 16 + hw/i2c/Makefile.objs|1

Re: [Qemu-devel] [PATCH] m25p80: fix test on blk_pread() return value

On 05/31/2016 04:26 PM, Eric Blake wrote: > On 05/31/2016 05:36 AM, Cédric Le Goater wrote: >> commit 243e6f69c129 ("m25p80: Switch to byte-based block access") >> replaced blk_read() calls with blk_pread() but return values are >> different. > > Shoot,

Re: [Qemu-devel] [PATCH] m25p80: fix test on blk_pread() return value

On 06/15/2016 09:57 AM, Kevin Wolf wrote: > Am 14.06.2016 um 18:02 hat Cédric Le Goater geschrieben: >> On 06/14/2016 10:38 AM, Kevin Wolf wrote: >>> Am 14.06.2016 um 10:02 hat Cédric Le Goater geschrieben: >>>>>> #4 0x7fa81c6694ac in bdrv_aligned_pwr

[Qemu-devel] [PATCH] m25p80: provide a realize to support late inits.

-by: Cédric Le Goater <c...@kaod.org> --- Should apply on top of : m25p80: fix test on blk_pread() return value https://lists.gnu.org/archive/html/qemu-devel/2016-05/msg05574.html hw/block/m25p80.c | 24 +--- 1 file changed, 17 insertions(+), 7 deletions(-) diff

Re: [Qemu-devel] [PATCH 6/9] m25p80: Introduce quad and equad modes.

On 06/15/2016 03:41 PM, marcin.krzemin...@nokia.com wrote: > From: Marcin Krzeminski > > Quad and Equad modes for Spansion and Macronix flash devices. > This commit also includes modification and new command to manipulate > quad mode (status registers and dedicated

Re: [Qemu-devel] [PATCH] m25p80: provide a realize to support late inits.

On 06/15/2016 04:20 PM, Paolo Bonzini wrote: > > > On 15/06/2016 16:00, Cédric Le Goater wrote: >> We also need to realize() the SSISlave part of the object. This is why >> the previous realize() ops is stored in M25P80Class and called in the >> object realize

Re: [Qemu-devel] [PATCH v2 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On 06/22/2016 04:46 AM, David Gibson wrote: > I'm not comfortable merging this until the openbios change is pulled > back into the qemu tree (submodule and pre-built binary). > > Again - sure you don't want to apply this with rfi still enabled for > 64-bit for now, letting the rest of this series

[Qemu-devel] [PATCH 0/4] ast2400: SMC controllers

/lastSuccessfulBuild/artifact/images/palmetto.pnor Thanks, Cédric Le Goater (4): ast2400: add SMC controllers (FMC and SPI) ast2400: add SPI flash slave object ast2400: create SPI flash slaves tests: add a m25p80 test hw/arm/ast2400.c| 31 +++ hw/arm/palmetto-bmc.c | 3

[Qemu-devel] [PATCH 1/4] ast2400: add SMC controllers (FMC and SPI)

-by: Cédric Le Goater <c...@kaod.org> --- hw/arm/ast2400.c| 31 + hw/ssi/Makefile.objs| 1 + hw/ssi/aspeed_smc.c | 300 include/hw/arm/ast2400.h| 3 + include/hw/ssi/aspeed_smc.h | 79 5 files c

[Qemu-devel] [PATCH 3/4] ast2400: create SPI flash slaves

he defaults provided by the specs. They can be changed with the Segment Address Register but this is not supported in the current implementation. Signed-off-by: Cédric Le Goater <c...@kaod.org> --- hw/arm/palmetto-bmc.c | 3 +++ hw/ssi

[Qemu-devel] [PATCH 2/4] ast2400: add SPI flash slave object

is sufficient to support Linux which only uses User Mode. Signed-off-by: Cédric Le Goater <c...@kaod.org> --- Is that the right approach or should we just use simple structs under AspeedSMCState and attach the memory region to the Aspeed SMC controller SysBus object ? Please advise.

[Qemu-devel] [PATCH 4/4] tests: add a m25p80 test

This test uses the palmetto platform and the AST2400 SPI controller to test the m25p80 flash module device model. The flash model is defined by the platform (n25q256a) and it would be nice to find way to control it, using a property probably. Signed-off-by: Cédric Le Goater <c...@kaod.

Re: [Qemu-devel] Odp.: [PATCH 6/9] m25p80: Introduce quad and equad modes.

On 06/15/2016 07:40 PM, Krzeminski, Marcin (Nokia - PL/Wroclaw) wrote: > > > W dniu 15.06.2016 o 16:25, Cédric Le Goater pisze: >> On 06/15/2016 03:41 PM, marcin.krzemin...@nokia.com wrote: >>> From: Marcin Krzeminski <marcin.krzemin...@nokia.com> >>>

Re: [Qemu-devel] [PATCH v2 1/5] m25p80: qdev-ify drive property

On 06/17/2016 02:32 PM, Paolo Bonzini wrote: > > > On 17/06/2016 14:15, Cédric Le Goater wrote: >> From: Paolo Bonzini <pbonz...@redhat.com> >> >> This allows specifying the property via -drive if=none and creating >> the flash device with -device. &g

Re: [Qemu-devel] [PATCH v2 06/10] m25p80: Introduce quad and equad modes.

gisters and dedicated commands). > This work is based on Pawel Lenkow work. > > Signed-off-by: Marcin Krzeminski <marcin.krzemin...@nokia.com> Reviewed-by: Cédric Le Goater <c...@kaod.org> Thanks, C. > --- > hw/block/m25p80.c | 70 > ++

Re: [Qemu-devel] [PATCH v2 08/10] m25p80: Fast read commands family changes.

nd decoding to functions. > > Signed-off-by: Marcin Krzeminski <marcin.krzemin...@nokia.com> Reviewed-by: Cédric Le Goater <c...@kaod.org> Thanks, it looks better. C. > --- > hw/block/m25p80.c | 145 > --

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On 06/17/2016 08:28 AM, David Gibson wrote: > On Fri, Jun 17, 2016 at 08:03:29AM +0200, Cédric Le Goater wrote: >> On 06/17/2016 07:54 AM, Cédric Le Goater wrote: >>> On 06/17/2016 04:27 AM, David Gibson wrote: >>>> On Thu, Jun 16, 2016 at 11:07:02AM +1000, David Gibs

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On 06/17/2016 09:10 AM, Thomas Huth wrote: > On 17.06.2016 08:03, Cédric Le Goater wrote: >> On 06/17/2016 07:54 AM, Cédric Le Goater wrote: >>> On 06/17/2016 04:27 AM, David Gibson wrote: >>>> On Thu, Jun 16, 2016 at 11:07:02AM +1000, David Gibson wrote: >>&g

Re: [Qemu-devel] [PATCH 3/4] ast2400: create SPI flash slaves

On 06/17/2016 12:11 PM, Paolo Bonzini wrote: > > > On 17/06/2016 10:35, Cédric Le Goater wrote: >> A set of SPI flash slaves is attached under the flash controllers of >> the palmetto platform. "n25q256a" flash modules are used for the BMC >> and &q

Re: [Qemu-devel] [PATCH v2 4/5] ast2400: create SPI flash slaves

On 06/20/2016 05:38 PM, Peter Maydell wrote: > On 17 June 2016 at 13:15, Cédric Le Goater <c...@kaod.org> wrote: >> A set of SPI flash slaves is attached under the flash controllers of >> the palmetto platform. "n25q256a" flash modules are used for the BMC &g

[Qemu-devel] [PATCH v2 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

shing.org> Reviewed-by: David Gibson <da...@gibson.dropbear.id.au> [clg: updated the commit log with the reference of the openbios fix ] Signed-off-by: Cédric Le Goater <c...@kaod.org> --- target-ppc/excp_helper.c | 51 +++- target-ppc/translate.

[Qemu-devel] [PATCH v2 00/10] rework exception model to support the HV mode

Hello, Here is a new set bringing more changes required for the powernv platform. The major one is the rework of the exception model to support the HV mode. It was tested with a pseries guest, KVM and TCG, and with a mac99 guest ! The next serie will cover a rework of XICS to support native

[Qemu-devel] [PATCH v2 07/10] ppc: Add real mode CI load/store instructions for P7 and P8

] Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: David Gibson <da...@gibson.dropbear.id.au> --- target-ppc/cpu.h| 4 ++- target-ppc/translate.c | 59 - target-ppc/translate_init.c | 6 +++-- 3 files chang

[Qemu-devel] [PATCH v2 05/10] ppc: Fix generation if ISI/DSI vs. HV mode

njamin Herrenschmidt <b...@kernel.crashing.org> Reviewed-by: David Gibson <da...@gibson.dropbear.id.au> [clg: Merged a fix on POWERPC_EXCP_HDSI fixing the condition on msr_hv, from Andrei Warkentin <andrey.warken...@gmail.com> ] Signed-off-by: Cédric Le Goater <c...@kaod.org>

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