On 4/22/2024 6:42 AM, Rajneesh Bhardwaj wrote:
> Tune coarse grain clock gating idle threshold and rlc idle timeout to
> achieve better kernel launch latency.
>
> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@amd.com>
Reviewed-by: Lijo Lazar <lijo.la...@amd.com>
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> index 835004187a58..813528fb4f2a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> @@ -2404,10 +2404,10 @@
> gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
> if (def != data)
> WREG32_SOC15(GC, GET_INST(GC, xcc_id),
> regRLC_CGTT_MGCG_OVERRIDE, data);
>
> - /* enable cgcg FSM(0x0000363F) */
> + /* CGCG Hysteresis: 400us */
> def = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
> regRLC_CGCG_CGLS_CTRL);
>
> - data = (0x36
> + data = (0x2710
> << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
> if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
> @@ -2416,10 +2416,10 @@
> gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
> if (def != data)
> WREG32_SOC15(GC, GET_INST(GC, xcc_id),
> regRLC_CGCG_CGLS_CTRL, data);
>
> - /* set IDLE_POLL_COUNT(0x00900100) */
> + /* set IDLE_POLL_COUNT(0x33450100)*/
> def = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
> regCP_RB_WPTR_POLL_CNTL);
> data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
> - (0x0090 <<
> CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
> + (0x3345 <<
> CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
> if (def != data)
> WREG32_SOC15(GC, GET_INST(GC, xcc_id),
> regCP_RB_WPTR_POLL_CNTL, data);
> } else {
