On Fri, May 3, 2024 at 4:45 AM Sunil Khatri <sunil.kha...@amd.com> wrote:
>
> add registers in the ip dump for CP headers in gfx10
>
> Signed-off-by: Sunil Khatri <sunil.kha...@amd.com>
Patches 1, 2 are:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 3171ed5e5af3..61c1e997f794 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -366,7 +366,14 @@ static const struct amdgpu_hwip_reg_entry
> gc_reg_list_10_1[] = {
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
> - SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST)
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),
> + /* cp header registers */
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP)
> };
>
> static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
> --
> 2.34.1
>
