hi dale,
thanks for helping out zhu yan and FAST.
dan
On Wed, Mar 7, 2018 at 5:14 AM, Gary, Dale E. <dale.e.g...@njit.edu> wrote:
> Hi Yan,
>
> This sounds like the problem we had until Matt Dexter and Dave MacMahon
> determined that some KatADC registers need to be set for correct ADC
> operation. Below is the python code we use to set them:
>
> addr = [0x0000, 0x0001, 0x0002, 0x0003, 0x0009, 0x000A,
> 0x000B, 0x000E, 0x000F]
> val = [0x7FFF, 0xBAFF, 0x007F, 0x807F, 0x03FF, 0x007F,
> 0x807F, 0x00FF, 0x007F]
> #val = [0x7FFF, 0xB2FF, 0x007F, 0x807F, 0x03FF, 0x007F,
> 0x807F, 0x00FF, 0x007F] # 300 MHz
> #if interleaved: val[4] = 0x23FF # Uncomment this line for
> interleaved mode
> for i in range(len(addr)):
> print('Setting ADC register %04Xh to 0x%04X' % (addr[i],
> val[i]))
> # Program both ZDOKs (this could be made smarter if
> needed).
> corr.katadc.spi_write_register(self.fpga, 0, addr[i],
> val[i])
> corr.katadc.spi_write_register(self.fpga, 1, addr[i],
> val[i])
>
> Note that at higher clock speeds, the value of the second register is
> changed (commented third line), as determined by Jack Hickish. If you want
> more detailed information, you will have to consult these folks, but I am
> optimistic that this will help you. This uses the older corr python
> module, but some equivalent command to spi_write_register() must exist in
> the more up-to-date casperfpga module.
>
> Regards,
> Dale
>
> On Wed, Mar 7, 2018 at 7:09 AM, 朱岩 <zhu...@nao.cas.cn> wrote:
>
>> Hi all,
>>
>> We have encountered some issue while using the KAT-7 KatADC on ROACH2.
>> Does anyone has experience in using KatADC on ROACH2 board?
>>
>> Below are what we got while test katadc on roach2.
>>
>> In attached pictures katadc-snap-r1817*.png,
>> This is a simulink model built by me to capture the sampling data from
>> Katadc,
>> The 2 Zdoks are all polulated with katadc board. The sampling clock is
>> 1GHz and
>> the input signals are all 5MHz sine wave. The FPGA clock is derived from
>> ADC0.
>> It is clear that there are something wrong with ZDOK1 katadc board.
>>
>> After that, I swapped these 2 cards, all captured signal are not good
>> this time,
>> as seen in katadc-snap-r1807-swapped.png.
>>
>> We also tested one single board(the bad one) connected in ZDOK0. And
>> found that
>> while feeding 1GHz sampling clock, the estimated fpga clock speed from
>> katcp_wrapper.py:est_brd_clk() is very unstable, as seen in
>> bad-card-fpga-clock.png.
>> And compare to the good board, good-card-fpga-clock.png
>>
>> This suggest some clock/timing issue with these board. We also double
>> check the sampling
>> clock and input signal, they are all correct.
>>
>> Then I try to lower down the sampling clock, and found while the sampling
>> clock is lower
>> than about 950MHz, the estimated fpga clock tends to be stable, but the
>> fpga clock speed
>> is /2 of sampling clock, not /4, which I think it should be /4. This was
>> very strange to me,
>> and might be a clue for further investigation.
>>
>> Any suggestion are welcome.
>>
>>
>> Thanks
>> Yan
>>
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