Hi Indrajit, I'm surprised that the Xilinx FIFO block doesn't give the option of having ports of two different widths. However, if it doesn't, the easiest thing to do might be to use a dual port RAM, which does allow the two interfaces to have different widths. If you can explain a bit more about what you're trying to achieve someone may already have a solution (for example, lots of designs have logic to turn N-bit data streams into 64-bit streams which can be used to feed the 10GbE block).
Cheers Jack On Thu, 25 Apr 2019 at 06:53, Indrajit Barve <indra...@iiap.res.in> wrote: > > Hello all, > > I would like to implement a FIFO with input port data type depth and width > of 2048 X 32 and output port data type 1024 X 64. Basically looking a similar > module like this > https://www.xilinx.com/support/documentation/application_notes/xapp261.pdf . > or how to implement / configure Data-Width Conversion for a FIFO on ROACH1 . > > Thanks > Indrajit > > -- > You received this message because you are subscribed to the Google Groups > "casper@lists.berkeley.edu" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to casper+unsubscr...@lists.berkeley.edu. > To post to this group, send email to casper@lists.berkeley.edu. -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To post to this group, send email to casper@lists.berkeley.edu.
