https://github.com/dtcxzyw created https://github.com/llvm/llvm-project/pull/76256
This patch adds support for `__builtin_riscv_cpop_32/64`, which are used by `riscv_bitmanip.h`. See also https://github.com/llvm/llvm-project/blob/04c473bea3e0f135432698fcaafab52e1fe1b5ec/clang/lib/Headers/riscv_bitmanip.h#L35-L60. Thank @Liaoshihua for reporting this! >From a69599fcda5f1a4df13ec0bfe3432ba39ef09246 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng <dtcxzyw2...@gmail.com> Date: Sat, 23 Dec 2023 01:21:39 +0800 Subject: [PATCH] [Clang][RISCV] Add missing support for __builtin_riscv_cpop_32/64 --- clang/include/clang/Basic/BuiltinsRISCV.def | 2 ++ clang/lib/CodeGen/CGBuiltin.cpp | 10 +++++++ clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c | 26 +++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def index 1528b18c82eade..1df1c53733cfa1 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.def +++ b/clang/include/clang/Basic/BuiltinsRISCV.def @@ -22,6 +22,8 @@ TARGET_BUILTIN(__builtin_riscv_clz_32, "UiUi", "nc", "zbb|xtheadbb") TARGET_BUILTIN(__builtin_riscv_clz_64, "UiUWi", "nc", "zbb|xtheadbb,64bit") TARGET_BUILTIN(__builtin_riscv_ctz_32, "UiUi", "nc", "zbb") TARGET_BUILTIN(__builtin_riscv_ctz_64, "UiUWi", "nc", "zbb,64bit") +TARGET_BUILTIN(__builtin_riscv_cpop_32, "UiUi", "nc", "zbb") +TARGET_BUILTIN(__builtin_riscv_cpop_64, "UiUWi", "nc", "zbb,64bit") // Zbc or Zbkc extension TARGET_BUILTIN(__builtin_riscv_clmul_32, "UiUiUi", "nc", "zbc|zbkc") diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 5081062da2862e..64210e76ed2218 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -20696,6 +20696,8 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_clz_64: case RISCV::BI__builtin_riscv_ctz_32: case RISCV::BI__builtin_riscv_ctz_64: + case RISCV::BI__builtin_riscv_cpop_32: + case RISCV::BI__builtin_riscv_cpop_64: case RISCV::BI__builtin_riscv_clmul_32: case RISCV::BI__builtin_riscv_clmul_64: case RISCV::BI__builtin_riscv_clmulh_32: @@ -20735,6 +20737,14 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, "cast"); return Result; } + case RISCV::BI__builtin_riscv_cpop_32: + case RISCV::BI__builtin_riscv_cpop_64: { + Value *Result = Builder.CreateUnaryIntrinsic(Intrinsic::ctpop, Ops[0]); + if (Result->getType() != ResultType) + Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/ true, + "cast"); + return Result; + } // Zbc case RISCV::BI__builtin_riscv_clmul_32: diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c index 3a421f8c6cd421..a5715e330172bd 100644 --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c @@ -82,3 +82,29 @@ unsigned int ctz_64(unsigned long a) { return __builtin_riscv_ctz_64(a); } #endif + +// RV32ZBB-LABEL: @cpop_32( +// RV32ZBB-NEXT: entry: +// RV32ZBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctpop.i32(i32 [[A:%.*]]) +// RV32ZBB-NEXT: ret i32 [[TMP0]] +// +// RV64ZBB-LABEL: @cpop_32( +// RV64ZBB-NEXT: entry: +// RV64ZBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctpop.i32(i32 [[A:%.*]]) +// RV64ZBB-NEXT: ret i32 [[TMP0]] +// +unsigned int cpop_32(unsigned int a) { + return __builtin_riscv_cpop_32(a); +} + +#if __riscv_xlen == 64 +// RV64ZBB-LABEL: @cpop_64( +// RV64ZBB-NEXT: entry: +// RV64ZBB-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctpop.i64(i64 [[A:%.*]]) +// RV64ZBB-NEXT: [[CAST:%.*]] = trunc i64 [[TMP0]] to i32 +// RV64ZBB-NEXT: ret i32 [[CAST]] +// +unsigned int cpop_64(unsigned long a) { + return __builtin_riscv_cpop_64(a); +} +#endif _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits