================ @@ -486,7 +486,8 @@ std::unique_ptr<TargetCodeGenInfo> createAIXTargetCodeGenInfo(CodeGenModule &CGM, bool Is64Bit); std::unique_ptr<TargetCodeGenInfo> -createPPC32TargetCodeGenInfo(CodeGenModule &CGM, bool SoftFloatABI); +createPPC32TargetCodeGenInfo(CodeGenModule &CGM, bool SoftFloatABI, + unsigned RLen); ---------------- Long5hot wrote:
I was not sure about hardcoding Register Width(RLen) **"32"** for RLen here.. https://github.com/llvm/llvm-project/pull/77732/files#diff-05339beb4a6cf7efdfc537984255dd372dcf1edd2d00eabed25831da4d1d0a9fR276 So i used similiar approach like, how RISC-V does to calculate Register Width here. PPC : https://github.com/llvm/llvm-project/pull/77732/files#diff-e724febedab9c1a2832bf2056d208ff02ddcb2e6f90b5a653afc9b19ac78a5d7R187 RISCV : https://github.com/llvm/llvm-project/pull/77732/files#diff-e724febedab9c1a2832bf2056d208ff02ddcb2e6f90b5a653afc9b19ac78a5d7L226 https://github.com/llvm/llvm-project/pull/77732 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits