=?utf-8?b?6YOd5bq36L6+?= <h...@bosc.ac.cn> Message-ID: In-Reply-To: <llvm.org/llvm/llvm-project/pull/90...@github.com>
camel-cdr wrote: The execution unit layout does not match the current XiangShan master. Has the final execution unit layout been decided on? [earlier layout](https://github.com/OpenXiangShan/XiangShan/blob/e25e4d90505c592524b410b127fe611ac49a3adf/src/main/scala/xiangshan/Parameters.scala#L355), which this PR seems to be based on: ``` VFEX0: VfaluCfg, VfmaCfg, VialuCfg, VimacCfg VFEX1: VipuCfg, VppuCfg, VfcvtCfg, F2vCfg, F2fCfg, F2iCfg, VSetRvfWvfCfg VFEX2: VfaluCfg, VfmaCfg, VialuCfg VFEX3: VfdivCfg, VidivCfg ``` [current master layout](https://github.com/OpenXiangShan/XiangShan/blob/2e61107/src/main/scala/xiangshan/Parameters.scala#L357): ``` VFEX0: VfmaCfg, VialuCfg, VimacCfg, VppuCfg VFEX1: VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg VFEX2: VfmaCfg, VialuCfg, F2vCfg VFEX3: VfaluCfg, VfcvtCfg VFEX4: VfdivCfg, VidivCfg VFEX5: VfdivCfg, VidivCfg ``` There even is a open branch that seperates the vpu and fpu pipelines: https://github.com/OpenXiangShan/XiangShan/blob/fp-split/src/main/scala/xiangshan/Parameters.scala#L365 I'd love to have proper scheduling support for kunminghu, but it currectly doesn't look like a stable target. BTW: Having two div, but only a single vppu seems like a bit of an odd choice. XuanTie C920 has two permutation execution units, and so do the more comparable ARM Neoverse N2 and AMD Zen1. https://github.com/llvm/llvm-project/pull/90392 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
