https://github.com/klensy created https://github.com/llvm/llvm-project/pull/91854
Similar to https://github.com/rust-lang/rust/pull/125007 This fixes few filecheck annotation typos across llvm repo. i **did not** checked if it passes test after that, so some help appreciated. >From 73dc4487a8a13a13f628857334afb25dcf2aa1f4 Mon Sep 17 00:00:00 2001 From: klensy <kle...@users.noreply.github.com> Date: Sat, 11 May 2024 14:26:52 +0300 Subject: [PATCH] llvm: fix few typos in filecheck tests clang: fix few typos in filecheck tests flang: fix few typos in filecheck tests and few more --- .../checkers/modernize/redundant-void-arg.cpp | 4 +- .../Analysis/analyzer-checker-option-help.c | 40 +++++++++---------- .../vtable-assume-load-address-space.cpp | 2 +- clang/test/CodeGenCXX/vtable-assume-load.cpp | 2 +- .../standard_conversion_sequences.hlsl | 6 +-- flang/test/Lower/HLFIR/maxloc.f90 | 2 +- flang/test/Lower/HLFIR/maxval.f90 | 2 +- flang/test/Lower/HLFIR/minloc.f90 | 2 +- flang/test/Lower/HLFIR/minval.f90 | 2 +- flang/test/Lower/HLFIR/sum.f90 | 2 +- flang/test/Lower/Intrinsics/adjustl.f90 | 2 +- flang/test/Lower/Intrinsics/adjustr.f90 | 2 +- flang/test/Lower/Intrinsics/fraction.f90 | 2 +- flang/test/Lower/polymorphic.f90 | 2 +- lld/test/ELF/linkerscript/orphan-phdrs2.test | 2 +- lld/test/ELF/ttext-tdata-tbss.s | 8 ++-- .../AArch64/sve-shuffle-broadcast.ll | 2 +- .../irreducible/diverged-entry-headers.ll | 2 +- .../CodeGen/AArch64/aarch64_tree_tests.ll | 4 +- llvm/test/CodeGen/AArch64/arm64_32-atomics.ll | 20 +++++----- ...tliner-retaddr-sign-diff-scope-same-key.ll | 2 +- .../stp-opt-with-renaming-undef-assert.mir | 2 +- llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 4 +- llvm/test/CodeGen/ARM/dsp-loop-indexing.ll | 2 +- .../test/CodeGen/Mips/optimizeAndPlusShift.ll | 18 ++++----- .../intel-usm-addrspaces.ll | 2 +- llvm/test/CodeGen/SystemZ/prefetch-04.ll | 2 +- llvm/test/CodeGen/X86/global-sections.ll | 4 +- .../X86/stack-folding-fp-avx512fp16.ll | 2 +- .../CodeGen/X86/stack-frame-layout-remarks.ll | 2 +- llvm/test/CodeGen/X86/tailregccpic.ll | 4 +- .../InstrRef/livedebugvalues_illegal_locs.mir | 2 +- llvm/test/MC/ARM/coff-relocations.s | 2 +- llvm/test/MC/Mips/expansion-jal-sym-pic.s | 12 +++--- llvm/test/Transforms/Inline/AArch64/binop.ll | 16 ++++---- .../Transforms/Inline/update_invoke_prof.ll | 2 +- .../InstCombine/lifetime-sanitizer.ll | 2 +- ...imal-epilog-vectorization-profitability.ll | 8 ++-- .../first-order-recurrence-complex.ll | 2 +- llvm/test/Transforms/LoopVectorize/memdep.ll | 2 +- ...wrapping-pointer-non-integral-addrspace.ll | 2 +- .../X86/good-prototype.ll | 2 +- .../PhaseOrdering/lifetime-sanitizer.ll | 2 +- llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll | 2 +- .../test/tools/dsymutil/ARM/dwarf5-macho.test | 26 ++++++------ llvm/test/tools/llvm-ar/replace-update.test | 2 +- mlir/test/Dialect/GPU/outlining.mlir | 2 +- 47 files changed, 120 insertions(+), 120 deletions(-) diff --git a/clang-tools-extra/test/clang-tidy/checkers/modernize/redundant-void-arg.cpp b/clang-tools-extra/test/clang-tidy/checkers/modernize/redundant-void-arg.cpp index 89bf7f04f5576..6cf59f91016df 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/modernize/redundant-void-arg.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/modernize/redundant-void-arg.cpp @@ -306,8 +306,8 @@ void gronk::bar(void) { // CHECK-MESSAGES: :[[@LINE-2]]:11: warning: {{.*}} in variable declaration // CHECK-FIXES: {{^ }}void (gronk::*p5){{$}} // CHECK-FIXES-NEXT: {{^ \($}} - // CHECK-FIXES-NExT: {{^ $}} - // CHECK-FIXES-NExT: {{^ \);$}} + // CHECK-FIXES-NEXT: {{^ $}} + // CHECK-FIXES-NEXT: {{^ \);$}} } // intentionally not LLVM style to check preservation of whitespace diff --git a/clang/test/Analysis/analyzer-checker-option-help.c b/clang/test/Analysis/analyzer-checker-option-help.c index 5f95569e58498..5e7531314f3ba 100644 --- a/clang/test/Analysis/analyzer-checker-option-help.c +++ b/clang/test/Analysis/analyzer-checker-option-help.c @@ -35,26 +35,26 @@ // // CHECK-STABLE: cplusplus.Move:WarnOn // CHECK-STABLE-SAME: (string) In non-aggressive mode, only warn -// CHECK-STABLLE: on use-after-move of local variables (or -// CHECK-STABLLE: local rvalue references) and of STL objects. -// CHECK-STABLLE: The former is possible because local variables -// CHECK-STABLLE: (or local rvalue references) are not tempting -// CHECK-STABLLE: their user to re-use the storage. The latter -// CHECK-STABLLE: is possible because STL objects are known -// CHECK-STABLLE: to end up in a valid but unspecified state -// CHECK-STABLLE: after the move and their state-reset methods -// CHECK-STABLLE: are also known, which allows us to predict -// CHECK-STABLLE: precisely when use-after-move is invalid. -// CHECK-STABLLE: Some STL objects are known to conform to -// CHECK-STABLLE: additional contracts after move, so they -// CHECK-STABLLE: are not tracked. However, smart pointers -// CHECK-STABLLE: specifically are tracked because we can -// CHECK-STABLLE: perform extra checking over them. In aggressive -// CHECK-STABLLE: mode, warn on any use-after-move because -// CHECK-STABLLE: the user has intentionally asked us to completely -// CHECK-STABLLE: eliminate use-after-move in his code. Values: -// CHECK-STABLLE: "KnownsOnly", "KnownsAndLocals", "All". -// CHECK-STABLLE: (default: KnownsAndLocals) +// CHECK-STABLE: on use-after-move of local variables (or +// CHECK-STABLE: local rvalue references) and of STL objects. +// CHECK-STABLE: The former is possible because local variables +// CHECK-STABLE: (or local rvalue references) are not tempting +// CHECK-STABLE: their user to re-use the storage. The latter +// CHECK-STABLE: is possible because STL objects are known +// CHECK-STABLE: to end up in a valid but unspecified state +// CHECK-STABLE: after the move and their state-reset methods +// CHECK-STABLE: are also known, which allows us to predict +// CHECK-STABLE: precisely when use-after-move is invalid. +// CHECK-STABLE: Some STL objects are known to conform to +// CHECK-STABLE: additional contracts after move, so they +// CHECK-STABLE: are not tracked. However, smart pointers +// CHECK-STABLE: specifically are tracked because we can +// CHECK-STABLE: perform extra checking over them. In aggressive +// CHECK-STABLE: mode, warn on any use-after-move because +// CHECK-STABLE: the user has intentionally asked us to completely +// CHECK-STABLE: eliminate use-after-move in his code. Values: +// CHECK-STABLE: "KnownsOnly", "KnownsAndLocals", "All". +// CHECK-STABLE: (default: KnownsAndLocals) // CHECK-STABLE-NOT: debug.AnalysisOrder:* // CHECK-DEVELOPER: debug.AnalysisOrder:* diff --git a/clang/test/CodeGenCXX/vtable-assume-load-address-space.cpp b/clang/test/CodeGenCXX/vtable-assume-load-address-space.cpp index d765fe94d9b08..00afc7e1862eb 100644 --- a/clang/test/CodeGenCXX/vtable-assume-load-address-space.cpp +++ b/clang/test/CodeGenCXX/vtable-assume-load-address-space.cpp @@ -109,7 +109,7 @@ void g(B *a) { a->foo(); } // CHECK3: call void @_ZN5test31CC1Ev(ptr // CHECK3: %[[CMP:.*]] = icmp eq ptr addrspace(1) %{{.*}}, getelementptr inbounds inrange(-24, 8) ({ [4 x ptr addrspace(1)] }, ptr addrspace(1) @_ZTVN5test31CE, i32 0, i32 0, i32 3) // CHECK3: call void @llvm.assume(i1 %[[CMP]]) -// CHECK3-LABLEL: } +// CHECK3-LABEL: } void test() { C c; g(&c); diff --git a/clang/test/CodeGenCXX/vtable-assume-load.cpp b/clang/test/CodeGenCXX/vtable-assume-load.cpp index 6ce07d0db1b15..21ed9233a74fa 100644 --- a/clang/test/CodeGenCXX/vtable-assume-load.cpp +++ b/clang/test/CodeGenCXX/vtable-assume-load.cpp @@ -111,7 +111,7 @@ void g(B *a) { a->foo(); } // CHECK3: call void @_ZN5test31CC1Ev(ptr // CHECK3: %[[CMP:.*]] = icmp eq ptr %{{.*}}, getelementptr inbounds inrange(-24, 8) ({ [4 x ptr] }, ptr @_ZTVN5test31CE, i32 0, i32 0, i32 3) // CHECK3: call void @llvm.assume(i1 %[[CMP]]) -// CHECK3-LABLEL: } +// CHECK3-LABEL: } void test() { C c; g(&c); diff --git a/clang/test/SemaHLSL/standard_conversion_sequences.hlsl b/clang/test/SemaHLSL/standard_conversion_sequences.hlsl index a0d398105f15d..693dc1a4a2dc7 100644 --- a/clang/test/SemaHLSL/standard_conversion_sequences.hlsl +++ b/clang/test/SemaHLSL/standard_conversion_sequences.hlsl @@ -4,9 +4,9 @@ void test() { // CHECK: VarDecl {{.*}} used f3 'vector<float, 3>':'float __attribute__((ext_vector_type(3)))' cinit - // CHECK-NEXt: ImplicitCastExpr {{.*}} 'vector<float, 3>':'float __attribute__((ext_vector_type(3)))' <VectorSplat> - // CHECK-NEXt: ImplicitCastExpr {{.*}} 'float' <FloatingCast> - // CHECK-NEXt: FloatingLiteral {{.*}} 'double' 1.000000e+00 + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'vector<float, 3>':'float __attribute__((ext_vector_type(3)))' <VectorSplat> + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'float' <FloatingCast> + // CHECK-NEXT: FloatingLiteral {{.*}} 'double' 1.000000e+00 vector<float,3> f3 = 1.0; // No warning for splatting to a vector from a literal. diff --git a/flang/test/Lower/HLFIR/maxloc.f90 b/flang/test/Lower/HLFIR/maxloc.f90 index 166a1b9db1724..dbcac8ccb1d28 100644 --- a/flang/test/Lower/HLFIR/maxloc.f90 +++ b/flang/test/Lower/HLFIR/maxloc.f90 @@ -86,7 +86,7 @@ subroutine maxloc5(s) ! CHECK-NEXT: hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<2xi32>, !fir.ref<!fir.array<2xi32>> ! CHECK-NEXT: hlfir.destroy %[[EXPR]] : !hlfir.expr<2xi32> ! CHECK-NEXT: return -! CHECK-nEXT: } +! CHECK-NEXT: } ! back argument as .true. subroutine maxloc_back(a, s) diff --git a/flang/test/Lower/HLFIR/maxval.f90 b/flang/test/Lower/HLFIR/maxval.f90 index 5adad286a77d2..7a4f52fc1c0d4 100644 --- a/flang/test/Lower/HLFIR/maxval.f90 +++ b/flang/test/Lower/HLFIR/maxval.f90 @@ -83,7 +83,7 @@ subroutine maxval5(s) ! CHECK-NEXT: hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<2xi32>, !fir.ref<!fir.array<2xi32>> ! CHECK-NEXT: hlfir.destroy %[[EXPR]] : !hlfir.expr<2xi32> ! CHECK-NEXT: return -! CHECK-nEXT: } +! CHECK-NEXT: } subroutine maxval6(a, s, d) integer, pointer :: d diff --git a/flang/test/Lower/HLFIR/minloc.f90 b/flang/test/Lower/HLFIR/minloc.f90 index f835cf54b2a73..45f2ef2d7f3b7 100644 --- a/flang/test/Lower/HLFIR/minloc.f90 +++ b/flang/test/Lower/HLFIR/minloc.f90 @@ -86,7 +86,7 @@ subroutine minloc5(s) ! CHECK-NEXT: hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<2xi32>, !fir.ref<!fir.array<2xi32>> ! CHECK-NEXT: hlfir.destroy %[[EXPR]] : !hlfir.expr<2xi32> ! CHECK-NEXT: return -! CHECK-nEXT: } +! CHECK-NEXT: } ! back argument as .true. subroutine minloc_back(a, s) diff --git a/flang/test/Lower/HLFIR/minval.f90 b/flang/test/Lower/HLFIR/minval.f90 index 01b0ce77e2d30..3382bd20b6652 100644 --- a/flang/test/Lower/HLFIR/minval.f90 +++ b/flang/test/Lower/HLFIR/minval.f90 @@ -83,7 +83,7 @@ subroutine minval5(s) ! CHECK-NEXT: hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<2xi32>, !fir.ref<!fir.array<2xi32>> ! CHECK-NEXT: hlfir.destroy %[[EXPR]] : !hlfir.expr<2xi32> ! CHECK-NEXT: return -! CHECK-nEXT: } +! CHECK-NEXT: } subroutine minval6(a, s, d) integer, pointer :: d diff --git a/flang/test/Lower/HLFIR/sum.f90 b/flang/test/Lower/HLFIR/sum.f90 index 339582088b032..aed567f73b6b1 100644 --- a/flang/test/Lower/HLFIR/sum.f90 +++ b/flang/test/Lower/HLFIR/sum.f90 @@ -83,7 +83,7 @@ subroutine sum5(s) ! CHECK-NEXT: hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<2xi32>, !fir.ref<!fir.array<2xi32>> ! CHECK-NEXT: hlfir.destroy %[[EXPR]] : !hlfir.expr<2xi32> ! CHECK-NEXT: return -! CHECK-nEXT: } +! CHECK-NEXT: } subroutine sum6(a, s, d) integer, pointer :: d diff --git a/flang/test/Lower/Intrinsics/adjustl.f90 b/flang/test/Lower/Intrinsics/adjustl.f90 index a8d004cd52665..4f5161b467298 100644 --- a/flang/test/Lower/Intrinsics/adjustl.f90 +++ b/flang/test/Lower/Intrinsics/adjustl.f90 @@ -1,6 +1,6 @@ ! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s -! CHECK-LABLE: adjustl_test +! CHECK-LABEL: adjustl_test subroutine adjustl_test character(len=12) :: adjust_str = ' 0123456789' ! CHECK: %[[strBox:.*]] = fir.alloca !fir.box<!fir.heap<!fir.char<1,?>>> diff --git a/flang/test/Lower/Intrinsics/adjustr.f90 b/flang/test/Lower/Intrinsics/adjustr.f90 index 07aa08c994586..92ebf313b6848 100644 --- a/flang/test/Lower/Intrinsics/adjustr.f90 +++ b/flang/test/Lower/Intrinsics/adjustr.f90 @@ -1,6 +1,6 @@ ! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s -! CHECK-LABLE: adjustr_test +! CHECK-LABEL: adjustr_test subroutine adjustr_test character(len=12) :: adjust_str = '0123456789 ' ! CHECK: %[[strBox:.*]] = fir.alloca !fir.box<!fir.heap<!fir.char<1,?>>> diff --git a/flang/test/Lower/Intrinsics/fraction.f90 b/flang/test/Lower/Intrinsics/fraction.f90 index f9fff725eb27a..3120e6f232ecb 100644 --- a/flang/test/Lower/Intrinsics/fraction.f90 +++ b/flang/test/Lower/Intrinsics/fraction.f90 @@ -1,7 +1,7 @@ ! RUN: bbc -emit-fir %s -o - | FileCheck %s ! FRACTION -! CHECK-LABE: fraction_test +! CHECK-LABEL: fraction_test subroutine fraction_test real(kind=4) :: x1 = 178.1387e-4 diff --git a/flang/test/Lower/polymorphic.f90 b/flang/test/Lower/polymorphic.f90 index 14ec8a06a964f..0f148947fea57 100644 --- a/flang/test/Lower/polymorphic.f90 +++ b/flang/test/Lower/polymorphic.f90 @@ -151,7 +151,7 @@ subroutine call_fct() ! CHECK-LABEL: func.func @_QMpolymorphic_testPtest_fct_ret_class() -> !fir.class<!fir.ptr<!fir.type<_QMpolymorphic_testTp1{a:i32,b:i32}>>> ! CHECK: return %{{.*}} : !fir.class<!fir.ptr<!fir.type<_QMpolymorphic_testTp1{a:i32,b:i32}>>> -! CHECK-lABEL: func.func @_QMpolymorphic_testPcall_fct() +! CHECK-LABEL: func.func @_QMpolymorphic_testPcall_fct() ! CHECK: %[[RESULT:.*]] = fir.alloca !fir.class<!fir.ptr<!fir.type<_QMpolymorphic_testTp1{a:i32,b:i32}>>> {bindc_name = ".result"} ! CHECK: %[[CALL_RES:.*]] = fir.call @_QMpolymorphic_testPtest_fct_ret_class() {{.*}}: () -> !fir.class<!fir.ptr<!fir.type<_QMpolymorphic_testTp1{a:i32,b:i32}>>> ! CHECK: fir.save_result %[[CALL_RES]] to %[[RESULT]] : !fir.class<!fir.ptr<!fir.type<_QMpolymorphic_testTp1{a:i32,b:i32}>>>, !fir.ref<!fir.class<!fir.ptr<!fir.type<_QMpolymorphic_testTp1{a:i32,b:i32}>>>> diff --git a/lld/test/ELF/linkerscript/orphan-phdrs2.test b/lld/test/ELF/linkerscript/orphan-phdrs2.test index c302e0e70b2bb..d75c76da87e81 100644 --- a/lld/test/ELF/linkerscript/orphan-phdrs2.test +++ b/lld/test/ELF/linkerscript/orphan-phdrs2.test @@ -12,7 +12,7 @@ # CHECK-NEXT: Type {{.*}} Flg Align # CHECK-NEXT: LOAD {{.*}} R E 0x # CHECK-NEXT: LOAD {{.*}} RW 0x -# CHECK-MEXT: LOAD {{.*}} R 0x +# CHECK-NEXT: LOAD {{.*}} R 0x # CHECK: Segment Sections... # CHECK-NEXT: 00 .text {{$}} diff --git a/lld/test/ELF/ttext-tdata-tbss.s b/lld/test/ELF/ttext-tdata-tbss.s index fb9c4d5131749..39d6506416808 100644 --- a/lld/test/ELF/ttext-tdata-tbss.s +++ b/lld/test/ELF/ttext-tdata-tbss.s @@ -45,10 +45,10 @@ # RUN: ld.lld -Ttext 0x201000 %t.o -o %t4 # RUN: llvm-readelf -S -l %t4 | FileCheck %s --check-prefix=USER3 # USER3: .text PROGBITS 0000000000201000 001000 000001 -# USER3-NEX: .rodata PROGBITS 0000000000202000 002000 000008 -# USER3-NEX: .aw PROGBITS 0000000000203000 003000 000008 -# USER3-NEX: .data PROGBITS 0000000000203008 003008 000008 -# USER3-NEX: .bss NOBITS 0000000000203010 003010 000008 +# USER3-NEXT: .rodata PROGBITS 0000000000202000 002000 000008 +# USER3-NEXT: .aw PROGBITS 0000000000203000 003000 000008 +# USER3-NEXT: .data PROGBITS 0000000000203008 003008 000008 +# USER3-NEXT: .bss NOBITS 0000000000203010 003010 000008 # USER3: Type # USER3-NEXT: PHDR 0x000040 0x0000000000200040 # USER3-NEXT: LOAD 0x000000 0x0000000000200000 diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll b/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll index a2526d9f5591a..c2aab35194831 100644 --- a/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll +++ b/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll @@ -31,7 +31,7 @@ define void @broadcast() #0{ ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = shufflevector <vscale x 8 x i1> undef, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %23 = shufflevector <vscale x 4 x i1> undef, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %24 = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer -; CHECK-NETX: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void %zero = shufflevector <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer %1 = shufflevector <vscale x 32 x i8> undef, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll index 335026dc9b62b..efad77b684a75 100644 --- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll +++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll @@ -90,7 +90,7 @@ S: br i1 %cond.uni, label %exit, label %T T: -; CHECK-NIT: DIVERGENT: %tt.phi = phi i32 +; CHECK-NOT: DIVERGENT: %tt.phi = phi i32 %tt.phi = phi i32 [ %ss, %S ], [ %a, %entry ] %tt = add i32 %b, 1 br label %P diff --git a/llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll b/llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll index 0a06765a8f75b..37cd3929be338 100644 --- a/llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll +++ b/llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target triple = "arm64--linux-gnu" ; FIXME: Misspelled CHECK-LABEL -; CHECK-LABLE: @aarch64_tree_tests_and +; CHECK-LABEL: @aarch64_tree_tests_and ; CHECK: .hword 32768 ; CHECK: .hword 32767 ; CHECK: .hword 4664 @@ -24,7 +24,7 @@ entry: } ; FIXME: Misspelled CHECK-LABEL -; CHECK-LABLE: @aarch64_tree_tests_or +; CHECK-LABEL: @aarch64_tree_tests_or ; CHECK: .hword 32768 ; CHECK: .hword 32766 ; CHECK: .hword 4664 diff --git a/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll b/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll index 0000262e833da..19b9205dc1786 100644 --- a/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll +++ b/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll @@ -2,70 +2,70 @@ ; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS define i8 @test_load_8(ptr %addr) { -; CHECK-LABAL: test_load_8: +; CHECK-LABEL: test_load_8: ; CHECK: ldarb w0, [x0] %val = load atomic i8, ptr %addr seq_cst, align 1 ret i8 %val } define i16 @test_load_16(ptr %addr) { -; CHECK-LABAL: test_load_16: +; CHECK-LABEL: test_load_16: ; CHECK: ldarh w0, [x0] %val = load atomic i16, ptr %addr acquire, align 2 ret i16 %val } define i32 @test_load_32(ptr %addr) { -; CHECK-LABAL: test_load_32: +; CHECK-LABEL: test_load_32: ; CHECK: ldar w0, [x0] %val = load atomic i32, ptr %addr seq_cst, align 4 ret i32 %val } define i64 @test_load_64(ptr %addr) { -; CHECK-LABAL: test_load_64: +; CHECK-LABEL: test_load_64: ; CHECK: ldar x0, [x0] %val = load atomic i64, ptr %addr seq_cst, align 8 ret i64 %val } define ptr @test_load_ptr(ptr %addr) { -; CHECK-LABAL: test_load_ptr: +; CHECK-LABEL: test_load_ptr: ; CHECK: ldar w0, [x0] %val = load atomic ptr, ptr %addr seq_cst, align 8 ret ptr %val } define void @test_store_8(ptr %addr) { -; CHECK-LABAL: test_store_8: +; CHECK-LABEL: test_store_8: ; CHECK: stlrb wzr, [x0] store atomic i8 0, ptr %addr seq_cst, align 1 ret void } define void @test_store_16(ptr %addr) { -; CHECK-LABAL: test_store_16: +; CHECK-LABEL: test_store_16: ; CHECK: stlrh wzr, [x0] store atomic i16 0, ptr %addr seq_cst, align 2 ret void } define void @test_store_32(ptr %addr) { -; CHECK-LABAL: test_store_32: +; CHECK-LABEL: test_store_32: ; CHECK: stlr wzr, [x0] store atomic i32 0, ptr %addr seq_cst, align 4 ret void } define void @test_store_64(ptr %addr) { -; CHECK-LABAL: test_store_64: +; CHECK-LABEL: test_store_64: ; CHECK: stlr xzr, [x0] store atomic i64 0, ptr %addr seq_cst, align 8 ret void } define void @test_store_ptr(ptr %addr) { -; CHECK-LABAL: test_store_ptr: +; CHECK-LABEL: test_store_ptr: ; CHECK: stlr wzr, [x0] store atomic ptr null, ptr %addr seq_cst, align 8 ret void diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll index a5757a70843a9..fa63df35ac857 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll +++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll @@ -28,7 +28,7 @@ define void @a() "sign-return-address"="all" { } define void @b() "sign-return-address"="non-leaf" { -; CHECK-LABE: b: // @b +; CHECK-LABEL: b: // @b ; V8A-NOT: hint #25 ; V83A-NOT: paciasp ; CHECK-NOT: .cfi_negate_ra_state diff --git a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir index 66d2067b531a3..bfdb1763776b4 100644 --- a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir +++ b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir @@ -12,7 +12,7 @@ # This test also checks that pairwise store STP is generated. -# CHECK-LABLE: test +# CHECK-LABEL: test # CHECK: bb.0: # CHECK-NEXT: liveins: $x0, $x17, $x18 # CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64) diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll index 50423c59eabe9..526d5c946ec7f 100644 --- a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll +++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll @@ -108,7 +108,7 @@ define amdgpu_kernel void @use_global_to_flat_addrspacecast(ptr addrspace(1) %pt } ; no-op -; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast: +; HSA-LABEL: {{^}}use_constant_to_flat_addrspacecast: ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] @@ -119,7 +119,7 @@ define amdgpu_kernel void @use_constant_to_flat_addrspacecast(ptr addrspace(4) % ret void } -; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast: +; HSA-LABEL: {{^}}use_constant_to_global_addrspacecast: ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]] ; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] ; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] diff --git a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll index 9fb64471e9881..892e66aed4e5f 100644 --- a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll +++ b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll @@ -22,7 +22,7 @@ ; CHECK-DEFAULT: ldr{{.*}}, #4] ; CHECK-DEFAULT: str{{.*}}, #4] ; CHECK-DEFAULT: ldr{{.*}}, #8]! -; CHECK-DEAFULT: ldr{{.*}}, #8]! +; CHECK-DEFAULT: ldr{{.*}}, #8]! ; CHECK-DEFAULT: str{{.*}}, #8]! ; CHECK-COMPLEX: ldr{{.*}}, #8]! diff --git a/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll b/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll index bf69adf6702f0..58920483e24bf 100644 --- a/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll +++ b/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll @@ -3,11 +3,11 @@ ; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64 define i32 @shl_32(i32 %a, i32 %b) { -; MIPS32-LABLE: shl_32: +; MIPS32-LABEL: shl_32: ; MIPS32: # %bb.0: ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: sllv $2, $4, $5 -; MIPS64-LABLE: shl_32: +; MIPS64-LABEL: shl_32: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: sll $2, $4, 0 @@ -19,11 +19,11 @@ define i32 @shl_32(i32 %a, i32 %b) { } define i32 @lshr_32(i32 %a, i32 %b) { -; MIPS32-LABLE: lshr_32: +; MIPS32-LABEL: lshr_32: ; MIPS32: # %bb.0: ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: srlv $2, $4, $5 -; MIPS64-LABLE: lshr_32: +; MIPS64-LABEL: lshr_32: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: sll $2, $4, 0 @@ -35,11 +35,11 @@ define i32 @lshr_32(i32 %a, i32 %b) { } define i32 @ashr_32(i32 %a, i32 %b) { -; MIPS32-LABLE: ashr_32: +; MIPS32-LABEL: ashr_32: ; MIPS32: # %bb.0: ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: srav $2, $4, $5 -; MIPS64-LABLE: ashr_32: +; MIPS64-LABEL: ashr_32: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: sll $2, $4, 0 @@ -51,7 +51,7 @@ define i32 @ashr_32(i32 %a, i32 %b) { } define i64 @shl_64(i64 %a, i64 %b) { -; MIPS64-LABLE: shl_64: +; MIPS64-LABEL: shl_64: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: jr $ra @@ -62,7 +62,7 @@ define i64 @shl_64(i64 %a, i64 %b) { } define i64 @lshr_64(i64 %a, i64 %b) { -; MIPS64-LABLE: lshr_64: +; MIPS64-LABEL: lshr_64: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: jr $ra @@ -73,7 +73,7 @@ define i64 @lshr_64(i64 %a, i64 %b) { } define i64 @ashr_64(i64 %a, i64 %b) { -; MIPS64-LABLE: ashr_64: +; MIPS64-LABEL: ashr_64: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: jr $ra diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll index b5df462bd8fa9..f5f1382a35fca 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll @@ -6,7 +6,7 @@ ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-: Capability USMStorageClassesINTEL -; CHECK-SPIRV-WITHOUT-NO: Capability USMStorageClassesINTEL +; CHECK-SPIRV-WITHOUT-NOT: Capability USMStorageClassesINTEL ; CHECK-SPIRV-EXT-DAG: %[[DevTy:[0-9]+]] = OpTypePointer DeviceOnlyINTEL %[[#]] ; CHECK-SPIRV-EXT-DAG: %[[HostTy:[0-9]+]] = OpTypePointer HostOnlyINTEL %[[#]] ; CHECK-SPIRV-DAG: %[[CrsWrkTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[#]] diff --git a/llvm/test/CodeGen/SystemZ/prefetch-04.ll b/llvm/test/CodeGen/SystemZ/prefetch-04.ll index 61a2a1460c583..10755bdb66eb5 100644 --- a/llvm/test/CodeGen/SystemZ/prefetch-04.ll +++ b/llvm/test/CodeGen/SystemZ/prefetch-04.ll @@ -6,7 +6,7 @@ ; ; CHECK-LABEL: for.body ; CHECK: call void @llvm.prefetch.p0(ptr %scevgep, i32 1, i32 3, i32 1 -; CHECK-not: call void @llvm.prefetch +; CHECK-NOT: call void @llvm.prefetch define void @fun(ptr nocapture %Src, ptr nocapture readonly %Dst) { entry: diff --git a/llvm/test/CodeGen/X86/global-sections.ll b/llvm/test/CodeGen/X86/global-sections.ll index b300fc87e38ab..0175eb23ce080 100644 --- a/llvm/test/CodeGen/X86/global-sections.ll +++ b/llvm/test/CodeGen/X86/global-sections.ll @@ -36,8 +36,8 @@ bb5: } ; LINUX: .size F2, -; LINUX-NEX: .cfi_endproc -; LINUX-NEX: .section .rodata,"a",@progbits +; LINUX-NEXT: .cfi_endproc +; LINUX-NEXT: .section .rodata,"a",@progbits ; LINUX-SECTIONS: .section .text.F2,"ax",@progbits ; LINUX-SECTIONS: .size F2, diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll index e4eca6b744af9..68bd9ce96608c 100644 --- a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll +++ b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll @@ -265,7 +265,7 @@ define i32 @stack_fold_fpclassph_mask(<32 x half> %a0, ptr %p) { } define i8 @stack_fold_fpclasssh(<8 x half> %a0) { - ;CHECK-LABEl: stack_fold_fpclasssh: + ;CHECK-LABEL: stack_fold_fpclasssh: ; CHECK-LABEL: stack_fold_fpclasssh: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill diff --git a/llvm/test/CodeGen/X86/stack-frame-layout-remarks.ll b/llvm/test/CodeGen/X86/stack-frame-layout-remarks.ll index d32a37efcb5a4..cd5edcf2ae502 100644 --- a/llvm/test/CodeGen/X86/stack-frame-layout-remarks.ll +++ b/llvm/test/CodeGen/X86/stack-frame-layout-remarks.ll @@ -35,7 +35,7 @@ entry: declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 ; BOTH: Function: cleanup_array -; BOTH-Next: Offset: [SP+4], Type: Protector, Align: 16, Size: 4 +; BOTH-NEXT: Offset: [SP+4], Type: Protector, Align: 16, Size: 4 ; DEBUG: a @ dot.c:13 ; STRIPPED-NOT: a @ dot.c:13 ; BOTH: Offset: [SP-4], Type: Spill, Align: 8, Size: 4 diff --git a/llvm/test/CodeGen/X86/tailregccpic.ll b/llvm/test/CodeGen/X86/tailregccpic.ll index f89c4ac4df599..a3a17d3b05397 100644 --- a/llvm/test/CodeGen/X86/tailregccpic.ll +++ b/llvm/test/CodeGen/X86/tailregccpic.ll @@ -13,12 +13,12 @@ entry: ret void } -;CHECK-LABLE: tail_call_regcall: +;CHECK-LABEL: tail_call_regcall: ;CHECK: # %bb.0: ;CHECK-NEXT: jmp __regcall3__func # TAILCALL ;CHECK-NEXT: .Lfunc_end0: -;CHECK-LABLE: __regcall3__func: +;CHECK-LABEL: __regcall3__func: ;CHECK: addl $_GLOBAL_OFFSET_TABLE_+({{.*}}), %ecx ;CHECK-NEXT: movl a0@GOT(%ecx), %ecx ;CHECK-NEXT: movl %eax, (%ecx) diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir index d4ed0fba2d7cd..d5fa1f1375ca0 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir @@ -43,7 +43,7 @@ debugValueSubstitutions: body: | bb.0.entry: successors: %bb.1, %bb.2 - ; CHECK-LABE: bb.0.entry: + ; CHECK-LABEL: bb.0.entry: $rax = MOV64ri 1, debug-instr-number 1, debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !17 diff --git a/llvm/test/MC/ARM/coff-relocations.s b/llvm/test/MC/ARM/coff-relocations.s index 5225b5e656762..16993cf7a8588 100644 --- a/llvm/test/MC/ARM/coff-relocations.s +++ b/llvm/test/MC/ARM/coff-relocations.s @@ -25,7 +25,7 @@ branch24t_1: bl target @ CHECK-ENCODING-LABEL: <branch24t_1>: -@ CHECK-ENCODING-NEXR: bl {{.+}} @ imm = #0 +@ CHECK-ENCODING-NEXT: bl {{.+}} @ imm = #0 .thumb_func branch20t: diff --git a/llvm/test/MC/Mips/expansion-jal-sym-pic.s b/llvm/test/MC/Mips/expansion-jal-sym-pic.s index c7b5ccc1880bd..1279de10d2503 100644 --- a/llvm/test/MC/Mips/expansion-jal-sym-pic.s +++ b/llvm/test/MC/Mips/expansion-jal-sym-pic.s @@ -227,12 +227,12 @@ local_label: # XO32-NEXT: .reloc ($tmp1), R_MIPS_JALR, weak_label # ELF-XO32: 3c 19 00 00 lui $25, 0 -# ELF-XO32-MEXT: R_MIPS_CALL_HI16 weak_label -# ELF-XO32-MEXT: 03 3c c8 21 addu $25, $25, $gp -# ELF-XO32-MEXT: 8f 39 00 00 lw $25, 0($25) -# ELF-XO32-MEXT: R_MIPS_CALL_LO16 weak_label -# ELF-XO32-MEXT: 03 20 f8 09 jalr $25 -# ELF-XO32-MEXT: R_MIPS_JALR weak_label +# ELF-XO32-NEXT: R_MIPS_CALL_HI16 weak_label +# ELF-XO32-NEXT: 03 3c c8 21 addu $25, $25, $gp +# ELF-XO32-NEXT: 8f 39 00 00 lw $25, 0($25) +# ELF-XO32-NEXT: R_MIPS_CALL_LO16 weak_label +# ELF-XO32-NEXT: 03 20 f8 09 jalr $25 +# ELF-XO32-NEXT: R_MIPS_JALR weak_label # N32: lw $25, %call16(weak_label)($gp) # encoding: [0x8f,0x99,A,A] # N32: # fixup A - offset: 0, value: %call16(weak_label), kind: fixup_Mips_CALL16 diff --git a/llvm/test/Transforms/Inline/AArch64/binop.ll b/llvm/test/Transforms/Inline/AArch64/binop.ll index eb882282820b8..86f4c045b5687 100644 --- a/llvm/test/Transforms/Inline/AArch64/binop.ll +++ b/llvm/test/Transforms/Inline/AArch64/binop.ll @@ -190,14 +190,14 @@ define i32 @shr(i32 %a, i32 %b) { define i1 @outer_and1(i1 %a) { ; check-label: @outer_and1( -; check-not: call i1 @and1 +; check-NOT: call i1 @and1 %c = call i1 @and1(i1 %a, i1 false) ret i1 %c } define i1 @outer_and2(i1 %a) { ; check-label: @outer_and2( -; check-not: call i1 @and1 +; check-NOT: call i1 @and1 %c = call i1 @and1(i1 %a, i1 true) ret i1 %c } @@ -212,7 +212,7 @@ define i1 @and1(i1 %a, i1 %b) { define i1 @outer_and3(i1 %a) { ; check-label: @outer_and3( -; check-not: call i1 @and2 +; check-NOT: call i1 @and2 %c = call i1 @and2(i1 %a) ret i1 %c } @@ -227,14 +227,14 @@ define i1 @and2(i1 %a) { define i1 @outer_or1(i1 %a) { ; check-label: @outer_or1( -; check-not: call i1 @or1 +; check-NOT: call i1 @or1 %c = call i1 @or1(i1 %a, i1 false) ret i1 %c } define i1 @outer_or2(i1 %a) { ; check-label: @outer_or2( -; check-not: call i1 @or1 +; check-NOT: call i1 @or1 %c = call i1 @or1(i1 %a, i1 true) ret i1 %c } @@ -249,7 +249,7 @@ define i1 @or1(i1 %a, i1 %b) { define i1 @outer_or3(i1 %a) { ; check-label: @outer_or3( -; check-not: call i1 @or2 +; check-NOT: call i1 @or2 %c = call i1 @or2(i1 %a) ret i1 %c } @@ -264,7 +264,7 @@ define i1 @or2(i1 %a) { define i1 @outer_xor1(i1 %a) { ; check-label: @outer_xor1( -; check-not: call i1 @xor +; check-NOT: call i1 @xor %c = call i1 @xor1(i1 %a, i1 false) ret i1 %c } @@ -279,7 +279,7 @@ define i1 @xor1(i1 %a, i1 %b) { define i1 @outer_xor3(i1 %a) { ; check-label: @outer_xor3( -; check-not: call i1 @xor +; check-NOT: call i1 @xor %c = call i1 @xor2(i1 %a) ret i1 %c } diff --git a/llvm/test/Transforms/Inline/update_invoke_prof.ll b/llvm/test/Transforms/Inline/update_invoke_prof.ll index f6b86dfe5bb1b..b5fb669c93cbd 100644 --- a/llvm/test/Transforms/Inline/update_invoke_prof.ll +++ b/llvm/test/Transforms/Inline/update_invoke_prof.ll @@ -66,7 +66,7 @@ ret: ; CHECK: invoke void @callee2( ; CHECK-NEXT: {{.*}} !prof ![[PROF3:[0-9]+]] -; CHECK-LABL: @callee( +; CHECK-LABEL: @callee( ; CHECK: invoke void %func( ; CHECK-NEXT: {{.*}} !prof ![[PROF4:[0-9]+]] ; CHECK: invoke void @callee1( diff --git a/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll b/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll index e379b32b45734..62573398fc16a 100644 --- a/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll +++ b/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll @@ -56,7 +56,7 @@ entry: call void @llvm.lifetime.start.p0(i64 1, ptr %text) call void @llvm.lifetime.end.p0(i64 1, ptr %text) - ; CHECK-NO: call void @llvm.lifetime + ; CHECK-NOT: call void @llvm.lifetime call void @foo(ptr %text) ; Keep alloca alive diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization-profitability.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization-profitability.ll index b88254e7b678d..2ee3efa6f8684 100644 --- a/llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization-profitability.ll +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization-profitability.ll @@ -10,7 +10,7 @@ target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" ; Do not vectorize epilogues for loops with minsize attribute -; CHECK-LABLE: @f1 +; CHECK-LABEL: @f1 ; CHECK-NOT: vector.main.loop.iter.check ; CHECK-NOT: vec.epilog.iter.check ; CHECK-NOT: vec.epilog.ph @@ -48,7 +48,7 @@ for.end: ; preds = %for.end.loopexit, % } ; Do not vectorize epilogues for loops with optsize attribute -; CHECK-LABLE: @f2 +; CHECK-LABEL: @f2 ; CHECK-NOT: vector.main.loop.iter.check ; CHECK-NOT: vec.epilog.iter.check ; CHECK-NOT: vec.epilog.ph @@ -86,7 +86,7 @@ for.end: ; preds = %for.end.loopexit, % } ; Do not vectorize the epilogue for loops with VF less than the default -epilogue-vectorization-minimum-VF of 16. -; CHECK-MIN-D-LABLE: @f3 +; CHECK-MIN-D-LABEL: @f3 ; CHECK-MIN-D-NOT: vector.main.loop.iter.check ; CHECK-MIN-D-NOT: vec.epilog.iter.check ; CHECK-MIN-D-NOT: vec.epilog.ph @@ -96,7 +96,7 @@ for.end: ; preds = %for.end.loopexit, % ; Specify a smaller minimum VF (via `-epilogue-vectorization-minimum-VF=4`) and ; make sure the epilogue gets vectorized in that case. -; CHECK-MIN-D-LABLE: @f3 +; CHECK-MIN-D-LABEL: @f3 ; CHECK-MIN-4: vector.main.loop.iter.check ; CHECK-MIN-4: vec.epilog.iter.check ; CHECK-MIN-4: vec.epilog.ph diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll index 95671078a7769..6b7be590c7c23 100644 --- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll +++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll @@ -335,7 +335,7 @@ define void @cannot_sink_reduction(i32 %x, ptr %ptr, i64 %tc) { -; CHECK-NET: ret void +; CHECK-NEXT: ret void entry: br label %preheader diff --git a/llvm/test/Transforms/LoopVectorize/memdep.ll b/llvm/test/Transforms/LoopVectorize/memdep.ll index b891b4312f18d..eb8c75741c0c0 100644 --- a/llvm/test/Transforms/LoopVectorize/memdep.ll +++ b/llvm/test/Transforms/LoopVectorize/memdep.ll @@ -244,7 +244,7 @@ for.end: ; RIGHTVF-LABEL: @pr34283 ; RIGHTVF: <4 x i64> -; WRONGVF-LABLE: @pr34283 +; WRONGVF-LABEL: @pr34283 ; WRONGVF-NOT: <8 x i64> @a = common local_unnamed_addr global [64 x i32] zeroinitializer, align 16 diff --git a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll index 430baa1cb4f8c..c426737963c52 100644 --- a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll +++ b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll @@ -13,7 +13,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:10:11:12:13" declare i64 @julia_steprange_last_4949() define void @"japi1_align!_9477"(ptr %arg) { -; LV-LAVEL: L26.lver.check +; LV-LABEL: L26.lver.check ; LV: [[OFMul:%[^ ]*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[Step:%[^ ]*]]) ; LV-NEXT: [[OFMulResult:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 0 ; LV-NEXT: [[OFMulOverflow:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 1 diff --git a/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll b/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll index e6c2a7e629a5d..cea752ad6898d 100644 --- a/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll +++ b/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll @@ -21,7 +21,7 @@ entry: define float @f_writeonly(float %val) { ; CHECK-LABEL: @f_writeonly( -; CHECK-NEXt: [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]] +; CHECK-NEXT: [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]] %res = tail call float @sqrtf(float %val) writeonly ret float %res } diff --git a/llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll b/llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll index 5f4d389265a86..3da71320d99c6 100644 --- a/llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll +++ b/llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll @@ -63,7 +63,7 @@ entry: call void @llvm.lifetime.start.p0(i64 1, ptr %text) call void @llvm.lifetime.end.p0(i64 1, ptr %text) - ; CHECK-NO: call void @llvm.lifetime + ; CHECK-NOT: call void @llvm.lifetime call void @foo(ptr %text) ; Keep alloca alive diff --git a/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll b/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll index bb370a6d1dfeb..7f7790cecb0eb 100644 --- a/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll +++ b/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll @@ -670,7 +670,7 @@ declare void @llvm.amdgcn.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i1) define amdgpu_cs void @test_buffer_atomic_fadd(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %offset, i1 %slc) { ; CHECK: immarg operand has non-immediate parameter ; CHECK-NEXT: i1 %slc - ; CHECK-ENXT: call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc) + ; CHECK-NEXT: call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc) call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc) ret void } diff --git a/llvm/test/tools/dsymutil/ARM/dwarf5-macho.test b/llvm/test/tools/dsymutil/ARM/dwarf5-macho.test index 5268324c2e100..be3a436bcf931 100644 --- a/llvm/test/tools/dsymutil/ARM/dwarf5-macho.test +++ b/llvm/test/tools/dsymutil/ARM/dwarf5-macho.test @@ -109,16 +109,16 @@ CHECK-NEXT: 0x0000000e: [DW_RLE_offset_pair ]: {{.*}}[0x[[RANGELIST_OFFSET_STAR CHECK-NEXT: 0x00000011: [DW_RLE_end_of_list ] CHECK: .debug_names contents: -CHECK-NEX:T Name Index @ 0x0 { -CHECK-NEX:T Header { -CHECK-NEX:T Length: 0x7C -CHECK-NEX:T Format: DWARF32 -CHECK-NEX:T Version: 5 -CHECK-NEX:T CU count: 1 -CHECK-NEX:T Local TU count: 0 -CHECK-NEX:T Foreign TU count: 0 -CHECK-NEX:T Bucket count: 3 -CHECK-NEX:T Name count: 3 -CHECK-NEX:T Abbreviations table size: 0xD -CHECK-NEX:T Augmentation: 'LLVM0700' -CHECK-NEX:T } +CHECK-NEXT: Name Index @ 0x0 { +CHECK-NEXT: Header { +CHECK-NEXT: Length: 0x7C +CHECK-NEXT: Format: DWARF32 +CHECK-NEXT: Version: 5 +CHECK-NEXT: CU count: 1 +CHECK-NEXT: Local TU count: 0 +CHECK-NEXT: Foreign TU count: 0 +CHECK-NEXT: Bucket count: 3 +CHECK-NEXT: Name count: 3 +CHECK-NEXT: Abbreviations table size: 0xD +CHECK-NEXT: Augmentation: 'LLVM0700' +CHECK-NEXT: } diff --git a/llvm/test/tools/llvm-ar/replace-update.test b/llvm/test/tools/llvm-ar/replace-update.test index c056565f144c5..498febdac0193 100644 --- a/llvm/test/tools/llvm-ar/replace-update.test +++ b/llvm/test/tools/llvm-ar/replace-update.test @@ -57,7 +57,7 @@ # MULTIPLE-SYM: symbolnew1 # MULTIPLE-SYM-NEXT: symbol2 -# MULTIPLE-SYM-NEXTs: symbolnew3 +# MULTIPLE-SYM-NEXT: symbolnew3 ## Replace newer members with multiple older files: # RUN: llvm-ar ruU %t/multiple.a %t/1.o %t/2.o diff --git a/mlir/test/Dialect/GPU/outlining.mlir b/mlir/test/Dialect/GPU/outlining.mlir index 5e4724c9d309c..47ebe326b5d12 100644 --- a/mlir/test/Dialect/GPU/outlining.mlir +++ b/mlir/test/Dialect/GPU/outlining.mlir @@ -123,7 +123,7 @@ llvm.func @launch_from_llvm_func() { llvm.return } -// CHECK-DL-LABLE: gpu.module @launch_from_llvm_func_kernel attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<index, 32 : i32>>} +// CHECK-DL-LABEL: gpu.module @launch_from_llvm_func_kernel attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<index, 32 : i32>>} // ----- _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
