On Tue, Jul 21, 2009 at 08:23:22AM -0600, Myles Watson wrote: > > It's actually just a plain byte-by-byte assignment in c, see > > src/lib/memset.c. > It would be interesting to see if you make it 4 bytes at a time if it is 4x > faster. > > > > > We found out after adding an extra MTRR over the flash chip, which did > > not > > > > change anything. > > > > > > Did you disable and re-enable the cache so that the settings take > > effect? > > > > Hmm, we tried adding it here > > > > src/cpu/amd/car/clear_init_ram.c > > > > in function set_init_ram_access, which already sets an mtrr. > I always wondered about that one. > > The thing that makes it hard to debug is that it will read back correctly > even if it hasn't taken effect. > > > Thanks - will see if I can try some of these things. > Good luck,
So - you're not going to believe this. Compiler issue. I was compiling with gcc (Ubuntu 4.3.3-5ubuntu4) 4.3.3 on 32 bit. I noticed that about one in every 10 burn/boot cycles or so, the slowness would not be there. So I switched back to gcc-3.4 (GCC) 3.4.6 (Ubuntu 3.4.6-8ubuntu2) on 32 bit, and it's gone altogether, every time. Is anyone else using gcc 4.3 (32 bit) to compile coreboot? Thanks! Ward. -- Ward Vandewege <w...@gnu.org> -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot