On Mon, Oct 15, 2018 at 6:42 AM Antony AbeePrakash X V <antonyabee.prakas...@lnttechservices.com> wrote: > > Hi Aron, > > > > I have tried giving iomem=relaxed to the kernel command line. But still I am > getting the same error. > > > > This time I tried with verbose option and the output is below > > $ ./cbmem -V -t > > > > Looking for coreboot table at 0 1048576 bytes. > > Mapping 1MB of physical memory at 0x0 (requested 0x0). > > Unmapping 1MB of virtual memory at 0x7fd372347000. > > Looking for coreboot table at f0000 1048576 bytes. > > Mapping 1MB of physical memory at 0xf0000 (requested 0xf0000). > > ... failed. Mapping 1052671B of physical memory at 0xef000. > > Failed to mmap /dev/mem: Operation not permitted > > > > Also could you please tell any method to measure the boot time ? Currently we > are measuring with the help of stop watch which may not accurate.
cbmem -t will provide it. What do you see in 'dmesg' ? Also, what do the e820 entries show? They should match below. 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000000fffffff: RAM 4. 0000000010000000-0000000012150fff: RESERVED 5. 0000000012151000-000000007a92cfff: RAM 6. 000000007a92d000-000000007affffff: CONFIGURATION TABLES 7. 000000007b000000-000000007fffffff: RESERVED 8. 00000000d0000000-00000000ffffffff: RESERVED How old of a cbmem utility are you using? don't understand where the 1MiB mappings are coming from. > > > > Thanks, > > Antony > > > > From: Aaron Durbin [mailto:adur...@google.com] > Sent: Friday, October 12, 2018 7:12 PM > To: Antony AbeePrakash X V <antonyabee.prakas...@lnttechservices.com> > Cc: Coreboot <coreboot@coreboot.org>; Dinesh Kumar > <dineshkumar.varadara...@lnttechservices.com> > Subject: Re: [coreboot] MRC in coreboot > > > > > > > > On Fri, Oct 12, 2018 at 4:38 AM Antony AbeePrakash X V > <antonyabee.prakas...@lnttechservices.com> wrote: > > Hi Aron, > > > > I am not able to get the cbmem timestamps. I am using cbmem utility to find > the timestamps. > > > > $ . /cbmem -t > > > > The above command gives the following error. > > > > Failed to mmap /dev/mem : Operation not permitted > > > > Could you please help on this? > > > > https://01.org/linuxgraphics/gfx-docs/drm/admin-guide/kernel-parameters.html > > > > Adding 'iomem=relaxed' to the kernel cmdline would fix that particular > problem. > > > > Note, with that current error, that you should see a PAT error in dmesg. > > > > > > Thanks & Regards, > > Antony > > From: Aaron Durbin [mailto:adur...@google.com] > Sent: Thursday, October 11, 2018 9:44 PM > To: Antony AbeePrakash X V <antonyabee.prakas...@lnttechservices.com> > Cc: Coreboot <coreboot@coreboot.org>; Dinesh Kumar > <dineshkumar.varadara...@lnttechservices.com> > Subject: Re: [coreboot] MRC in coreboot > > > > cbmem timstamps will be needed. > > > > Looks like FSP is manipulating the tsc: > > BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 4291539104 exit 0 > > > > I have a hard time believing that took 4291 seconds. > > > > On Thu, Oct 11, 2018 at 10:11 AM Antony AbeePrakash X V > <antonyabee.prakas...@lnttechservices.com> wrote: > > Hi Aaron, > > PFA the console log for your reference. > > Please look into this and provide feedback. > > Thanks, > Antony > > -----Original Message----- > From: Aaron Durbin [mailto:adur...@google.com] > Sent: Thursday, October 11, 2018 7:27 PM > To: Antony AbeePrakash X V <antonyabee.prakas...@lnttechservices.com> > Cc: Coreboot <coreboot@coreboot.org>; Dinesh Kumar > <dineshkumar.varadara...@lnttechservices.com> > Subject: Re: [coreboot] MRC in coreboot > > On Thu, Oct 11, 2018 at 3:24 AM Antony AbeePrakash X V > <antonyabee.prakas...@lnttechservices.com> wrote: > > > > Hi All, > > > > We are able to achieve the memory initialization time reduction. Now we > > have achieved the boot time as 5sec until the Postcode 0xf8 (entry into Elf > > boot). > > > > We have reduced the unwanted codes. We would like to reduce the boot time > > to less than 2sec. > > > > Could anyone please tell what can be done further ? > > You're going to need to post more information (cbmem timings and console > logs). > > > > > Thanks, > > Antony > > > > -----Original Message----- > > From: Aaron Durbin [mailto:adur...@google.com] > > Sent: Wednesday, September 05, 2018 7:39 PM > > To: Antony AbeePrakash X V <antonyabee.prakas...@lnttechservices.com> > > Cc: Coreboot <coreboot@coreboot.org> > > Subject: Re: [coreboot] MRC in coreboot > > > > On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V > > <antonyabee.prakas...@lnttechservices.com> wrote: > > > > > > Hi, > > > > > > > > > > > > We are developing coreboot for Apollo lake custom board. MRC training > > > data save is enabled in FSP using Binary configuration tool. > > > > > > > > > > > > But we are getting logs like, > > > > > > > > > > > > No MRC cache found. > > > > > > MRC SeCUmaSize memory size from SeC ... 0 > > > > > > MRC Parameters not valid. Status is Success > > > > > > MRC:CpuMemoryTest Successful! > > > > > > Saving MRC data using CSE through HECI interface > > > > I have never seen this path used in coreboot. This line above is saying CSE > > is responsible for saving and retrieving training data. In coreboot we use > > the main processor to save and restore. I suggest reading over the UPD > > parameters and ensure they match with our typical use cases. BCT tool > > enabling 'training data save' sounds like it's enabling CSE path. > > > > > > > > Try to find MRC training data HOB. > > > > > > No MRC training data found, perform data save via HECI. > > > > > > Saved MRC training data with status (0x80000003) > > > > > > > > > > > > It seems that MRC data is not found and saved. Also I found that there > > > are options to add MRC file path and mrc.bin in menuconfig. The only > > > option I have is save cached MRC settings. > > > > > > > > > > > > What this mrc.bin will do? > > > > > > How to add the mrc.bin in coreboot? > > > > > > > > > > > > Please explain on this. > > > > > > > > > > > > Thanks & Regards, > > > > > > Antony > > > > > > > > > > > > L&T Technology Services Ltd > > > > > > www.LntTechservices.com > > > > > > This Email may contain confidential or privileged information for the > > > intended recipient (s). If you are not the intended recipient, please do > > > not use or disseminate the information, notify the sender and delete it > > > from your system. > > > > > > -- > > > coreboot mailing list: coreboot@coreboot.org > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > L&T Technology Services Ltd > > > > www.LntTechservices.com<http://www.lnttechservices.com/> > > > > This Email may contain confidential or privileged information for the > > intended recipient (s). If you are not the intended recipient, please do > > not use or disseminate the information, notify the sender and delete it > > from your system. > L&T Technology Services Ltd > > www.LntTechservices.com<http://www.lnttechservices.com/> > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do not > use or disseminate the information, notify the sender and delete it from your > system. > > L&T Technology Services Ltd > > www.LntTechservices.com > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do not > use or disseminate the information, notify the sender and delete it from your > system. > > L&T Technology Services Ltd > > www.LntTechservices.com > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do not > use or disseminate the information, notify the sender and delete it from your > system. -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
