On Mon, 8 Nov 2021 13:18:07 +0530 "Naresh G. Solanki" <naresh.solanki.2...@gmail.com> wrote:
> Since the hang happens in Linux, can you in some way get Linux kernel log > to understand the cause like soft lockup or panic message. > No. > Also are you saying irrespective of serirq enable/disable, hang is seen? > > UART works properly in coreboot stages? Everyting works in cold boot or after a power cycle. UART tx does not need irq, codeboot doesn't read uart, so it works. Seabios and syslinux do polls, so they can work. > > On Mon, 8 Nov, 2021, 1:02 pm Lance Zhao, <lance.z...@gmail.com> wrote: > > > https://u8209486.ct.sendgrid.net/ls/click?upn=5-2BjrOL6Sde2a9aQLMiEgaLzceDV6ek3hr5PekV6loyqk65QWgl6iFUXTzf0xmiYdJQqz2O-2BmNofuvhc-2BSUW42g-3D-3DQK4h_L-2FDzr14mnrsJO5b1wX1hp9b1MAQygl7x-2B74RAaH2cn2k5PC3U9oOnKn4hExV-2FWbSoIC1hox-2BZ4-2B0KG0N5l-2BurrwvZ-2FUkvQYEMwmNTgsNqPB6SzAT4IrETNX1EIYiQNwEq5zh02K9uKWvS2Aziixg3mHLtGWAwizUW3YuNDTcGW7B8Vx6biZKem35D86EOq0SDpICxS-2BZDYtiPnDFxRjD9g-3D-3D > > Have similar implementation on braswell, so as long as sc_init get > > executed in ramstage the serial irq mode programming shall be working. > > > > Zhiwen Zheng <zhi...@40701.xyz> 于2021年11月6日周六 下午6:29写道： > > > >> I add the following code to sc_init() in southcluster.c to enable SERIRQ, > >> and it works as expected when doing cold boot. With SERIRQ enabled, the > >> uart in superio can function correctly, and I can login into the linux > >> serial console. But after a reboot initiated from linux cmdline, the linux > >> boot hang in getty serial(same as without SERIRQ enabled), only a power > >> cycle can resolve the issue. I take the following code from coreboot-4.11 > >> fsp-baytrail. I also tried the check_for_warm_reset() in bootblock.c to > >> hardreset the machine, but the check condition in that procedure doesn't > >> catch this situation, linux reset by default use keyboard controller > >> seemingly. > >> > >> u32 *oic = (u32 *)(ILB_BASE_ADDRESS + 0x60); > >> u8 *serirq_cntl = (u8 *)(ILB_BASE_ADDRESS + 0x10); > >> > >> > >> /* Enable SERIRQ */ > >> write32(oic, (read32(oic) | (1 << 12))); > >> /* Enable continuous mode */ > >> write8(serirq_cntl, (1 << 7)); > >> _______________________________________________ > >> coreboot mailing list -- coreboot@coreboot.org > >> To unsubscribe send an email to coreboot-le...@coreboot.org > >> > > _______________________________________________ > > coreboot mailing list -- coreboot@coreboot.org > > To unsubscribe send an email to coreboot-le...@coreboot.org > > _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
