ChangeLog | 34 ++++++++
debian/NEWS | 4 -
debian/changelog | 4 -
src/atombios_crtc.c | 3
src/atombios_output.c | 4 -
src/legacy_crtc.c | 6 -
src/radeon.h | 8 --
src/radeon_atombios.c | 4 -
src/radeon_driver.c | 194 +++++++++++++++++++++-----------------------------
9 files changed, 125 insertions(+), 136 deletions(-)
New commits:
commit 900831dc787cce3cb797d22f94c2d4fae9014ea0
Author: Brice Goglin <[EMAIL PROTECTED]>
Date: Sun Mar 2 13:23:12 2008 +0100
Prepare changelog for upload
diff --git a/debian/NEWS b/debian/NEWS
index 969ae2b..a6f60b0 100644
--- a/debian/NEWS
+++ b/debian/NEWS
@@ -1,10 +1,10 @@
-xserver-xorg-video-ati (1:6.8.1~git20080301.1f6a2300-1) UNRELEASED; urgency=low
+xserver-xorg-video-ati (1:6.8.1~git20080302.a4398ac3-1) experimental;
urgency=low
* The 'ati' Xorg driver module does not contain the 'r128' and 'mach64'
submodule anymore. Users of Rage or Mach boards should replace
Driver 'ati' with 'r128' or 'mach64' in their /etc/X11/xorg.conf.
- -- Brice Goglin <[EMAIL PROTECTED]> Sat, 01 Mar 2008 22:58:35 +0100
+ -- Brice Goglin <[EMAIL PROTECTED]> Sun, 02 Mar 2008 13:22:03 +0100
xserver-xorg-video-ati (1:6.7.197-1) unstable; urgency=low
diff --git a/debian/changelog b/debian/changelog
index 3f47acd..b15593d 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-xserver-xorg-video-ati (1:6.8.1~git20080301.1f6a2300-1) UNRELEASED; urgency=low
+xserver-xorg-video-ati (1:6.8.1~git20080302.a4398ac3-1) experimental;
urgency=low
* New upstream snapshot, after r128 and mach64 got split out.
+ Depends on xserver-xorg-video-r128 and xserver-xorg-video-mach64.
@@ -7,7 +7,7 @@ xserver-xorg-video-ati (1:6.8.1~git20080301.1f6a2300-1)
UNRELEASED; urgency=low
* Bump Standards-Version: to 3.7.3, no change needed.
* Remove XS- prefix to Vcs-Browser and Vcs-Git fields.
- -- Brice Goglin <[EMAIL PROTECTED]> Sat, 01 Mar 2008 23:03:35 +0100
+ -- Brice Goglin <[EMAIL PROTECTED]> Sun, 02 Mar 2008 13:20:59 +0100
xserver-xorg-video-ati (1:6.8.0-1) unstable; urgency=low
commit e356fcf95a0c5335ad40c7c05b35f65b4e7a4e62
Author: Brice Goglin <[EMAIL PROTECTED]>
Date: Sun Mar 2 13:22:59 2008 +0100
Update to latest upstream snapshot
diff --git a/ChangeLog b/ChangeLog
index e65cce3..6614356 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,37 @@
+commit a4398ac3ad77216f2c8aa628425bef5f2912a0a9
+Author: Alex Deucher <[EMAIL PROTECTED](none)>
+Date: Sat Mar 1 18:52:26 2008 -0500
+
+ RS6xx: change isIGP checks to CHIP_FAMILY_RS690
+
+ these paths are only relevant on RS6xx chips
+
+commit 67d4d04836c05293b844bc505f303cfb04c0f8a4
+Author: Alex Deucher <[EMAIL PROTECTED](none)>
+Date: Sat Mar 1 18:33:18 2008 -0500
+
+ RADEON: use xf86SetDesiredModes() in screeninit and enterVT
+
+ this should restore the proper output state on VT switches
+
+commit be0858a84fbdf74c0b844f462933a221d48c707d
+Author: Maciej Cencora <[EMAIL PROTECTED]>
+Date: Sat Mar 1 18:11:58 2008 -0500
+
+ RADEON: remove driver rec copies of mc info, use save rec directly
+
+ info->mc_* were used and the immediately copied into info->ModeReg
+ ones. Just use the ModeReg copies directly.
+
+commit dd8ee1b444f4b973a1e0fadca5f943f2162b5e94
+Author: Alex Deucher <[EMAIL PROTECTED](none)>
+Date: Sat Mar 1 16:23:51 2008 -0500
+
+ RADEON: memmap rework 1
+
+ Don't restore memmap regs on every mode switch.
+ Just do memmap save/restore/setup on server start and VT switch.
+
commit 1f6a23000001f3d1c21b5c04f94714a8caa7aa8b
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Sat Mar 1 15:53:42 2008 -0500
commit a4398ac3ad77216f2c8aa628425bef5f2912a0a9
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Sat Mar 1 18:52:26 2008 -0500
RS6xx: change isIGP checks to CHIP_FAMILY_RS690
these paths are only relevant on RS6xx chips
diff --git a/src/atombios_output.c b/src/atombios_output.c
index fb3cb3e..da3f533 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -393,7 +393,7 @@ dfp_disable_dither(xf86OutputPtr output, int device)
OUTREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL, 0); /* TMDSA */
break;
case ATOM_DEVICE_DFP2_SUPPORT:
- if (info->IsIGP)
+ if (info->ChipFamily == CHIP_FAMILY_RS690)
OUTREG(AVIVO_DDIA_BIT_DEPTH_CONTROL, 0); /* DDIA */
else
OUTREG(AVIVO_DVOA_BIT_DEPTH_CONTROL, 0); /* DVO */
@@ -609,7 +609,7 @@ atombios_output_mode_set(xf86OutputPtr output,
atombios_output_tmds1_setup(output, adjusted_mode);
dfp_disable_dither(output, ATOM_DEVICE_DFP1_SUPPORT);
} else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) {
- if (info->IsIGP)
+ if (info->ChipFamily == CHIP_FAMILY_RS690)
atombios_ddia_setup(output, adjusted_mode);
else
atombios_external_tmds_setup(output, adjusted_mode);
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 351939e..1da5e5c 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1754,7 +1754,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable
(ScrnInfoPtr pScrn)
(i == ATOM_DEVICE_TV2_INDEX) ||
(i == ATOM_DEVICE_CV_INDEX))
info->BiosConnector[i].ddc_i2c.valid = FALSE;
- else if (info->IsIGP) {
+ else if (info->ChipFamily == CHIP_FAMILY_RS690) {
/* IGP DFP ports use non-standard gpio entries */
if ((i == ATOM_DEVICE_DFP2_INDEX) || (i == ATOM_DEVICE_DFP3_INDEX))
info->BiosConnector[i].ddc_i2c =
@@ -1769,7 +1769,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable
(ScrnInfoPtr pScrn)
if (i == ATOM_DEVICE_DFP1_INDEX)
info->BiosConnector[i].TMDSType = TMDS_INT;
else if (i == ATOM_DEVICE_DFP2_INDEX) {
- if (info->IsIGP)
+ if (info->ChipFamily == CHIP_FAMILY_RS690)
info->BiosConnector[i].TMDSType = TMDS_DDIA;
else
info->BiosConnector[i].TMDSType = TMDS_EXT;
commit 67d4d04836c05293b844bc505f303cfb04c0f8a4
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Sat Mar 1 18:33:18 2008 -0500
RADEON: use xf86SetDesiredModes() in screeninit and enterVT
this should restore the proper output state on VT switches
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 853ec8c..e41906c 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -3031,9 +3031,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int hasDRI = 0;
- int i;
#ifdef RENDER
int subPixelOrder = SubPixelUnknown;
char* s;
@@ -3342,28 +3340,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* xf86CrtcRotate() accesses pScrn->pScreen */
pScrn->pScreen = pScreen;
-#if 1
- for (i = 0; i < xf86_config->num_crtc; i++) {
- xf86CrtcPtr crtc = xf86_config->crtc[i];
-
- /* Mark that we'll need to re-set the mode for sure */
- memset(&crtc->mode, 0, sizeof(crtc->mode));
- if (!crtc->desiredMode.CrtcHDisplay) {
- crtc->desiredMode = *RADEONCrtcFindClosestMode (crtc,
pScrn->currentMode);
- crtc->desiredRotation = RR_Rotate_0;
- crtc->desiredX = 0;
- crtc->desiredY = 0;
- }
-
- if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation,
crtc->desiredX, crtc->desiredY))
- return FALSE;
-
- }
-#else
- /* seems to do the wrong thing on some cards??? */
if (!xf86SetDesiredModes (pScrn))
return FALSE;
-#endif
RADEONSaveScreen(pScreen, SCREEN_SAVER_ON);
@@ -4967,8 +4945,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- int i;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONEnterVT\n");
@@ -5021,22 +4997,8 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
RADEONRestoreSurfaces(pScrn, info->ModeReg);
- for (i = 0; i < xf86_config->num_crtc; i++) {
- xf86CrtcPtr crtc = xf86_config->crtc[i];
- /* Mark that we'll need to re-set the mode for sure */
- memset(&crtc->mode, 0, sizeof(crtc->mode));
- if (!crtc->desiredMode.CrtcHDisplay) {
- crtc->desiredMode = *RADEONCrtcFindClosestMode (crtc,
pScrn->currentMode);
- crtc->desiredRotation = RR_Rotate_0;
- crtc->desiredX = 0;
- crtc->desiredY = 0;
- }
-
- if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation,
- crtc->desiredX, crtc->desiredY))
- return FALSE;
-
- }
+ if (!xf86SetDesiredModes(pScrn))
+ return FALSE;
/* this will get XVideo going again, but only if XVideo was initialised
during server startup (hence the info->adaptor if). */
commit be0858a84fbdf74c0b844f462933a221d48c707d
Author: Maciej Cencora <[EMAIL PROTECTED]>
Date: Sat Mar 1 18:11:58 2008 -0500
RADEON: remove driver rec copies of mc info, use save rec directly
info->mc_* were used and the immediately copied into info->ModeReg
ones. Just use the ModeReg copies directly.
diff --git a/src/radeon.h b/src/radeon.h
index 913dd51..b00d1e2 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -355,9 +355,6 @@ typedef struct {
unsigned long BIOSAddr; /* BIOS physical address */
CARD32 fbLocation;
CARD32 gartLocation;
- CARD32 mc_fb_location;
- CARD32 mc_agp_location;
- CARD32 mc_agp_location_hi;
void *MMIO; /* Map of MMIO region */
void *FB; /* Map of frame buffer */
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 7f10b4a..853ec8c 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1209,31 +1209,15 @@ static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn)
return TRUE;
}
-static void
-RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
- RADEONInfoPtr info)
-{
- save->mc_fb_location = info->mc_fb_location;
- save->mc_agp_location = info->mc_agp_location;
-
- if (IS_AVIVO_VARIANT) {
- save->mc_agp_location_hi = info->mc_agp_location_hi;
- } else {
- save->display_base_addr = info->fbLocation;
- save->display2_base_addr = info->fbLocation;
- save->ov0_base_addr = info->fbLocation;
- }
-}
-
-static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
+static void RADEONInitMemoryMap(ScrnInfoPtr pScrn, RADEONSavePtr save)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
CARD32 mem_size;
CARD32 aper_size;
- radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP,
&info->mc_fb_location,
- &info->mc_agp_location,
&info->mc_agp_location_hi);
+ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP,
&save->mc_fb_location,
+ &save->mc_agp_location,
&save->mc_agp_location_hi);
/* We shouldn't use info->videoRam here which might have been clipped
* but the real video RAM instead
@@ -1264,13 +1248,13 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
if (info->ChipFamily != CHIP_FAMILY_RS690) {
if (info->IsIGP)
- info->mc_fb_location = INREG(RADEON_NB_TOM);
+ save->mc_fb_location = INREG(RADEON_NB_TOM);
else
#ifdef XF86DRI
/* Old DRI has restrictions on the memory map */
if ( info->directRenderingEnabled &&
info->pKernelDRMVersion->version_minor < 10 )
- info->mc_fb_location = (mem_size - 1) & 0xffff0000U;
+ save->mc_fb_location = (mem_size - 1) & 0xffff0000U;
else
#endif
{
@@ -1298,19 +1282,19 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
aper0_base &= ~(mem_size - 1);
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- info->mc_fb_location = (aper0_base >> 24) |
+ save->mc_fb_location = (aper0_base >> 24) |
(((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
- ErrorF("mc fb loc is %08x\n", (unsigned
int)info->mc_fb_location);
+ ErrorF("mc fb loc is %08x\n", (unsigned
int)save->mc_fb_location);
} else {
- info->mc_fb_location = (aper0_base >> 16) |
+ save->mc_fb_location = (aper0_base >> 16) |
((aper0_base + mem_size - 1) & 0xffff0000U);
}
}
}
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
+ info->fbLocation = (save->mc_fb_location & 0xffff) << 24;
} else {
- info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
+ info->fbLocation = (save->mc_fb_location & 0xffff) << 16;
}
/* Just disable the damn AGP apertures for now, it may be
* re-enabled later by the DRM
@@ -1318,22 +1302,27 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
if (IS_AVIVO_VARIANT) {
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) &
0xff0000);
+ OUTREG(R600_HDP_NONSURFACE_BASE, (save->mc_fb_location << 16) &
0xff0000);
} else {
- OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
+ OUTREG(AVIVO_HDP_FB_LOCATION, save->mc_fb_location);
}
- info->mc_agp_location = 0x003f0000;
- } else
- info->mc_agp_location = 0xffffffc0;
+ save->mc_agp_location = 0x003f0000;
+ } else {
+ save->mc_agp_location = 0xffffffc0;
+ save->display_base_addr = info->fbLocation;
+ save->display2_base_addr = info->fbLocation;
+ save->ov0_base_addr = info->fbLocation;
+ }
+
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONInitMemoryMap() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
" mem_size : 0x%08x\n", (unsigned)mem_size);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location);
+ " MC_FB_LOCATION : 0x%08x\n", (unsigned)save->mc_fb_location);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
" MC_AGP_LOCATION : 0x%08x\n",
- (unsigned)info->mc_agp_location);
+ (unsigned)save->mc_agp_location);
}
static void RADEONGetVRamType(ScrnInfoPtr pScrn)
@@ -1342,7 +1331,7 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn)
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
CARD32 tmp;
-
+
if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300) ||
(INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30)))
info->IsDDR = TRUE;
@@ -3146,10 +3135,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* Initialize the memory map, this basically calculates the values
* we'll use later on for MC_FB_LOCATION & MC_AGP_LOCATION
*/
- RADEONInitMemoryMap(pScrn);
-
- /* copy saved memmap regs to saved mode regs */
- RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
+ RADEONInitMemoryMap(pScrn, info->ModeReg);
/* write any changes we made */
RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
@@ -3783,9 +3769,9 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr
pScrn, RADEONSavePtr save)
return;
radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp,
&agp_hi);
-
- if (fb != info->mc_fb_location || agp != info->mc_agp_location ||
- agp_hi || info->mc_agp_location_hi)
+
+ if (fb != save->mc_fb_location || agp != save->mc_agp_location ||
+ agp_hi || save->mc_agp_location_hi)
changed = 1;
if (changed) {
@@ -3793,21 +3779,28 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr
pScrn, RADEONSavePtr save)
"DRI init changed memory map, adjusting ...\n");
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
" MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n",
- (long unsigned int)info->mc_fb_location, (long unsigned
int)fb);
+ (long unsigned int)save->mc_fb_location, (long unsigned
int)fb);
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
" MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n",
- (long unsigned int)info->mc_agp_location, (long unsigned
int)agp);
- info->mc_fb_location = fb;
- info->mc_agp_location = agp;
+ (long unsigned int)save->mc_agp_location, (long unsigned
int)agp);
+ save->mc_fb_location = fb;
+ save->mc_agp_location = agp;
+ save->mc_agp_location_hi = agp_hi;
if (info->ChipFamily >= CHIP_FAMILY_R600)
- info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
+ info->fbLocation = (save->mc_fb_location & 0xffff) << 24;
else
- info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
+ info->fbLocation = (save->mc_fb_location & 0xffff) << 16;
+
+ if (!IS_AVIVO_VARIANT) {
+ save->display_base_addr = info->fbLocation;
+ save->display2_base_addr = info->fbLocation;
+ save->ov0_base_addr = info->fbLocation;
+ }
info->dst_pitch_offset =
(((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
<< 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
- RADEONInitMemMapRegisters(pScrn, save, info);
+
RADEONRestoreMemMapRegisters(pScrn, save);
}
@@ -3841,7 +3834,7 @@ static void RADEONRestoreSurfaces(ScrnInfoPtr pScrn,
RADEONSavePtr restore)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
unsigned int surfnr;
-
+
for ( surfnr = 0; surfnr < 8; surfnr++ ) {
OUTREG(RADEON_SURFACE0_INFO + 16 * surfnr,
restore->surfaces[surfnr][0]);
OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr,
restore->surfaces[surfnr][1]);
@@ -3902,7 +3895,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
color_pattern = R300_SURF_TILE_COLOR_MACRO;
} else {
color_pattern = R200_SURF_TILE_COLOR_MACRO;
- }
+ }
#ifdef XF86DRI
if (info->directRenderingInited) {
drmRadeonSurfaceFree drmsurffree;
@@ -3947,7 +3940,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
if (retvalue < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"drm: could not allocate surface for front buffer!\n");
-
+
if ((info->have3DWindows) && (!info->noBackBuffer)) {
drmsurfalloc.address = info->backOffset;
retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
commit dd8ee1b444f4b973a1e0fadca5f943f2162b5e94
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Sat Mar 1 16:23:51 2008 -0500
RADEON: memmap rework 1
Don't restore memmap regs on every mode switch.
Just do memmap save/restore/setup on server start and VT switch.
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index bc2df18..f7d9c37 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -330,9 +330,6 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay,
adjusted_mode->CrtcVDisplay,
adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal,
adjusted_mode->Flags);
- RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
- RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
-
if (IS_AVIVO_VARIANT) {
radeon_crtc->fb_width = mode->CrtcHDisplay;
radeon_crtc->fb_height = pScrn->virtualY;
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index 06ad60c..dec14a4 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -1693,8 +1693,6 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr
mode,
}
- ErrorF("init memmap\n");
- RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
ErrorF("init common\n");
RADEONInitCommonRegisters(info->ModeReg, info);
@@ -1748,8 +1746,6 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr
mode,
}
}
- ErrorF("restore memmap\n");
- RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
ErrorF("restore common\n");
RADEONRestoreCommonRegisters(pScrn, info->ModeReg);
@@ -1773,7 +1769,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr
mode,
radeon_update_tv_routing(pScrn, info->ModeReg);
if (info->DispPriority)
- RADEONInitDispBandwidth(pScrn);
+ RADEONInitDispBandwidth(pScrn);
if (info->tilingEnabled != tilingOld) {
/* need to redraw front buffer, I guess this can be considered a hack ?
*/
diff --git a/src/radeon.h b/src/radeon.h
index 9c83a4f..913dd51 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -817,8 +817,6 @@ extern Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr
output);
extern Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output);
extern Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output);
-extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
RADEONSavePtr restore);
extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
@@ -840,9 +838,6 @@ extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr
pScrn,
extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
RADEONSavePtr restore);
-extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr save,
- RADEONInfoPtr info);
extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
extern Bool RADEONI2cInit(ScrnInfoPtr pScrn);
extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn);
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 6a168a5..7f10b4a 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -125,6 +125,8 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn,
RADEONSavePtr save);
#ifdef XF86DRI
static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
#endif
+static void
+RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
extern DisplayModePtr
RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode);
@@ -1207,7 +1209,8 @@ static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn)
return TRUE;
}
-void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
+static void
+RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
RADEONInfoPtr info)
{
save->mc_fb_location = info->mc_fb_location;
@@ -1307,7 +1310,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
if (info->ChipFamily >= CHIP_FAMILY_R600) {
info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
} else {
- info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
}
/* Just disable the damn AGP apertures for now, it may be
* re-enabled later by the DRM
@@ -1319,9 +1322,9 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
} else {
OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
}
- info->mc_agp_location = 0x003f0000;
+ info->mc_agp_location = 0x003f0000;
} else
- info->mc_agp_location = 0xffffffc0;
+ info->mc_agp_location = 0xffffffc0;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONInitMemoryMap() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -3145,6 +3148,12 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
*/
RADEONInitMemoryMap(pScrn);
+ /* copy saved memmap regs to saved mode regs */
+ RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
+
+ /* write any changes we made */
+ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
+
/* empty the surfaces */
unsigned char *RADEONMMIO = info->MMIO;
unsigned int j;
@@ -3279,7 +3288,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"[drm] failed to enable new memory map\n");
RADEONDRICloseScreen(pScreen);
- info->directRenderingEnabled = FALSE;
+ info->directRenderingEnabled = FALSE;
}
}
#endif
@@ -3339,7 +3348,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR;
else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone;
PictureSetSubpixelOrder (pScreen, subPixelOrder);
- }
+ }
#endif
pScrn->vtSema = TRUE;
@@ -3406,7 +3415,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) {
- /* we need to re-calculate bandwidth because of AGPMode difference.
*/
+ /* we need to re-calculate bandwidth because of AGPMode difference.
*/
RADEONInitDispBandwidth(pScrn);
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
@@ -3544,8 +3553,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
}
/* Write memory mapping registers */
-void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore)
+static void
+RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
@@ -3615,7 +3625,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
} else {
OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location <<
16) & 0xff0000);
}
-
+
/* Reset the engine and HDP */
RADEONEngineReset(pScrn);
}
@@ -3665,7 +3675,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
| RADEON_CRTC2_DISP_REQ_EN_B);
}
- /* Make sure the chip settles down (paranoid !) */
+ /* Make sure the chip settles down (paranoid !) */
usleep(100000);
/* Wait for MC idle */
@@ -4640,7 +4650,7 @@ void RADEONRestore(ScrnInfoPtr pScrn)
#endif
/* to restore console mode, DAC registers should be set after every other
registers are set,
- * otherwise,we may get blank screen
+ * otherwise,we may get blank screen
*/
if (IS_AVIVO_VARIANT)
avivo_restore_vga_regs(pScrn, restore);
@@ -4703,7 +4713,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode,
int flags)
if (info->allowColorTiling) {
info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ?
FALSE : TRUE;
-#ifdef XF86DRI
+#ifdef XF86DRI
if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld))
{
RADEONSAREAPrivPtr pSAREAPriv;
if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING,
(info->tilingEnabled ? 1 : 0)) < 0)
@@ -4986,17 +4996,38 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
RADEONWaitForIdleMMIO(pScrn);
if (info->IsMobility && !IS_AVIVO_VARIANT) {
- if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE))
{
+ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
RADEONSetDynamicClock(pScrn, 1);
- } else {
+ } else {
RADEONSetDynamicClock(pScrn, 0);
- }
+ }
}
if (IS_R300_VARIANT || IS_RV100_VARIANT)
RADEONForceSomeClocks(pScrn);
pScrn->vtSema = TRUE;
+
+#ifdef XF86DRI
+ if (info->directRenderingEnabled) {
+ if (info->cardType == CARD_PCIE &&
+ info->pKernelDRMVersion->version_minor >= 19 &&
+ info->FbSecureSize) {
+ /* we need to backup the PCIE GART TABLE from fb memory */
+ memcpy(info->FB + info->pciGartOffset, info->pciGartBackup,
info->pciGartSize);
+ }
+
+ /* get the DRI back into shape after resume */
+ RADEONDRISetVBlankInterrupt (pScrn, TRUE);
+ RADEONDRIResume(pScrn->pScreen);
+ RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
+
+ } else
+#endif
+ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
+
+ RADEONRestoreSurfaces(pScrn, info->ModeReg);
+
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
/* Mark that we'll need to re-set the mode for sure */
@@ -5014,22 +5045,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
}
- RADEONRestoreSurfaces(pScrn, info->ModeReg);
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- if (info->cardType == CARD_PCIE &&
info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize)
- {
- /* we need to backup the PCIE GART TABLE from fb memory */
- memcpy(info->FB + info->pciGartOffset, info->pciGartBackup,
info->pciGartSize);
- }
-
- /* get the DRI back into shape after resume */
- RADEONDRISetVBlankInterrupt (pScrn, TRUE);
- RADEONDRIResume(pScrn->pScreen);
- RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
-
- }
-#endif
/* this will get XVideo going again, but only if XVideo was initialised
during server startup (hence the info->adaptor if). */
if (info->adaptor)
@@ -5045,7 +5060,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
}
#endif
- // pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
return TRUE;
}
@@ -5067,11 +5081,12 @@ void RADEONLeaveVT(int scrnIndex, int flags)
DRILock(pScrn->pScreen, 0);
RADEONCP_STOP(pScrn, info);
- if (info->cardType == CARD_PCIE &&
info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize)
- {
- /* we need to backup the PCIE GART TABLE from fb memory */
- memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset),
info->pciGartSize);
- }
+ if (info->cardType == CARD_PCIE &&
+ info->pKernelDRMVersion->version_minor >= 19 &&
+ info->FbSecureSize) {
+ /* we need to backup the PCIE GART TABLE from fb memory */
+ memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset),
info->pciGartSize);
+ }
/* Make sure 3D clients will re-upload textures to video RAM */
if (info->textureSize) {
--
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