[Bug target/105052] Incorrect constraint on SSSE3 split patterns with MMX operands

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105052

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by H.J. Lu <h...@gcc.gnu.org>:

https://gcc.gnu.org/g:40e7524ada2f09ec80d8083b9608a10ed516d8fe

commit r10-10514-g40e7524ada2f09ec80d8083b9608a10ed516d8fe
Author: H.J. Lu <hjl.to...@gmail.com>
Date:   Thu Mar 24 21:41:12 2022 -0700

    x86: Use x constraint on SSSE3 patterns with MMX operands

    Since PHADDW/PHADDD/PHADDSW/PHSUBW/PHSUBD/PHSUBSW/PSIGNB/PSIGNW/PSIGND
    have no AVX512 version, replace the "Yv" register constraint with the
    "x" register constraint.

            PR target/105052
            * config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3):
            Replace "Yv" with "x".
            (ssse3_ph<plusminus_mnemonic>dv2si3): Likewise.
            (ssse3_psign<mode>3): Likewise.

    (cherry picked from commit 99591cf43fc1da0fb72b3da02ba937ba30bd2bf2)