[Bug target/111634] RISC-V vector: ICE RTL check: expected code 'reg', have 'lo_sum' in rhs_regno, at rtl.h:1934

[patrick at rivosinc dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111634

--- Comment #1 from Patrick O'Neill <patrick at rivosinc dot com> ---
Comment on attachment 56011
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56011
-freport-bug output

>// Target: riscv64-unknown-linux-gnu
>// Configured with: 
>/scratch/tc-testing/rtl-checking-testsuite/build-rv64gcv/../gcc/configure 
>--target=riscv64-unknown-linux-gnu --prefix=/
>// Thread model: posix
>// Supported LTO compression algorithms: zlib zstd
>// gcc version 14.0.0 20230928 (experimental) (g8552dcd8e44)
>//
>// during RTL pass: expand
>// ../gcc/gcc/testsuite/gcc.dg/pr109417.c: In function 'main':
>// ../gcc/gcc/testsuite/gcc.dg/pr109417.c:17:17: internal compiler error: RTL 
>check: expected code 'reg', have 'lo_sum' in rhs_regno, at rtl.h:1934
>// 0x956453 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, 
>char const*)
>//      ../../../gcc/gcc/rtl.cc:770
>// 0x9833f5 rhs_regno(rtx_def const*)
>//      ../../../gcc/gcc/rtl.h:1934
>// 0x985924 rhs_regno(rtx_def const*)
>//      ../../../gcc/gcc/config/riscv/riscv.cc:2058
>// 0x985924 riscv_legitimize_address
>//      ../../../gcc/gcc/config/riscv/riscv.cc:2045
>// 0xf58089 memory_address_addr_space(machine_mode, rtx_def*, unsigned char)
>//      ../../../gcc/gcc/explow.cc:477
>// 0xf3e6ba change_address_1
>//      ../../../gcc/gcc/emit-rtl.cc:2294
>// 0xf40d7c offset_address(rtx_def*, rtx_def*, unsigned long)
>//      ../../../gcc/gcc/emit-rtl.cc:2532
>// 0xf8a321 expand_assignment(tree_node*, tree_node*, bool)
>//      ../../../gcc/gcc/expr.cc:5734
>// 0xe5c075 expand_gimple_stmt_1
>//      ../../../gcc/gcc/cfgexpand.cc:3946
>// 0xe5c075 expand_gimple_stmt
>//      ../../../gcc/gcc/cfgexpand.cc:4044
>// 0xe61927 expand_gimple_basic_block
>//      ../../../gcc/gcc/cfgexpand.cc:6100
>// 0xe63bd6 execute
>//      ../../../gcc/gcc/cfgexpand.cc:6835
>// Please submit a full bug report, with preprocessed source.
>// Please include the complete backtrace with any bug report.
>// See <https://gcc.gnu.org/bugs/> for instructions.
>
>// 
>/scratch/tc-testing/rtl-checking-testsuite/build-rv64gcv/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/cc1
> -quiet -imultilib lib64/lp64d ../gcc/gcc/testsuite/gcc.dg/pr109417.c -quiet 
>-dumpbase pr109417.c -dumpbase-ext .c -march=rv64gc -mabi=lp64d 
>-mcmodel=medlow -mtune=rocket -misa-spec=20191213 
>-march=rv64imafdc_zicsr_zifencei -O3 -fdiagnostics-color=never 
>-fno-diagnostics-show-caret -fno-diagnostics-show-line-numbers 
>-fdiagnostics-urls=never -fdiagnostics-path-format=separate-events 
>-fdiagnostics-text-art-charset=none -freport-bug -o - -frandom-seed=0 
>-fdump-noaddr
>
># 0 "../gcc/gcc/testsuite/gcc.dg/pr109417.c"
># 0 "<built-in>"
># 0 "<command-line>"
># 1 
>"/scratch/tc-testing/rtl-checking-testsuite/build-rv64gcv/sysroot/usr/include/stdc-predef.h"
> 1 3 4
># 0 "<command-line>" 2
># 1 "../gcc/gcc/testsuite/gcc.dg/pr109417.c"
>
>
>
>int printf(const char *, ...);
>int c, d, *e, f[1][2], g;
>int main() {
>  int h = 0, *a = &h, **b[1] = {&a};
>  while (e)
>    while (g) {
>    L:
>      for (h = 0; h < 2; h++) {
>        while (d)
>          for (*e = 0; *e < 1;)
>            printf("0");
>        while (c)
>          ;
>        f[g][h] = 0;
>      }
>    }
>  if (h)
>    goto L;
>  return 0;
>}