https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111378
--- Comment #4 from Jeffrey A. Law <law at gcc dot gnu.org> --- Whether or not this is an optimization or a pessimization is dependent on the target -- some targets can express the constant trivially in a branch conditions, others can not. Some targets have barrel shifters, others do not. In some cases the constant might get hoisted out of a loop, reducing the cost, but increasing register pressure, etc. If you look at a typical RISC target the transformation just trades constant construction for a shift. For constants that can be constructed in a single instruction neither sequence is inherently faster than the other. However, the shift sequence has an additional data dependency relative to the constant construction approach, so the shifted input approach would be considered slightly less desirable. For RISC-V we can construct any power of two constant in a single instruction if we have the zbs extension (which should be common in modern implementations). I suspect it would not be profitable on MIPS or PPC either as I think they have branches with ordered comparisons of two registers and the ability to construct 2^n in a single instrution. aarch64 seems to be the one target where this could be the helpful based on c#1. I guess it doesn't have branches with ordered comparisons of two registers and instead has to do an explicit comparison. Anyway, just wanted to get various thoughts recorded.
