https://gcc.gnu.org/g:3afcb04bd7d444b4c6547ad98668c2a6a7f37a21
commit r14-10054-g3afcb04bd7d444b4c6547ad98668c2a6a7f37a21 Author: Pan Li <pan2...@intel.com> Date: Sat Apr 20 22:37:56 2024 +0800 Revert "RISC-V: Fix overlap group incorrect overlap on v0" This reverts commit 018ba3ac952bed4ae01344c060360f13f7cc084a. Diff: --- gcc/config/riscv/vector.md | 268 ++++++++++----------- .../gcc.target/riscv/rvv/base/pr112431-34.c | 101 -------- 2 files changed, 134 insertions(+), 235 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 8a727e2ea41..2a6ab979588 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -2254,70 +2254,70 @@ ;; DEST eew is greater than SOURCE eew. (define_insn "@pred_indexed_<order>load<mode>_x2_greater_eew" - [(set (match_operand:VEEWEXT2 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VEEWEXT2 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") (if_then_else:VEEWEXT2 (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEEWEXT2 - [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") (mem:BLK (scratch)) - (match_operand:<VINDEX_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")] ORDER) - (match_operand:VEEWEXT2 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand:<VINDEX_DOUBLE_TRUNC> 4 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")] ORDER) + (match_operand:VEEWEXT2 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vl<order>xei<double_trunc_sew>.v\t%0,(%z3),%4%p1" [(set_attr "type" "vld<order>x") (set_attr "mode" "<MODE>") - (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) (define_insn "@pred_indexed_<order>load<mode>_x4_greater_eew" - [(set (match_operand:VEEWEXT4 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VEEWEXT4 0 "register_operand" "=vr, vr, vr, vr, ?&vr, ?&vr") (if_then_else:VEEWEXT4 (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEEWEXT4 - [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ") (mem:BLK (scratch)) - (match_operand:<VINDEX_QUAD_TRUNC> 4 "register_operand" "W43,W43,W43,W43,W86,W86,W86,W86, vr, vr")] ORDER) - (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand:<VINDEX_QUAD_TRUNC> 4 "register_operand" " W43, W43, W86, W86, vr, vr")] ORDER) + (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vl<order>xei<quad_trunc_sew>.v\t%0,(%z3),%4%p1" [(set_attr "type" "vld<order>x") (set_attr "mode" "<MODE>") - (set_attr "group_overlap" "W43,W43,W43,W43,W86,W86,W86,W86,none,none")]) + (set_attr "group_overlap" "W43,W43,W86,W86,none,none")]) (define_insn "@pred_indexed_<order>load<mode>_x8_greater_eew" - [(set (match_operand:VEEWEXT8 0 "register_operand" "=vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VEEWEXT8 0 "register_operand" "=vr, vr, ?&vr, ?&vr") (if_then_else:VEEWEXT8 (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEEWEXT8 - [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ") + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ") (mem:BLK (scratch)) - (match_operand:<VINDEX_OCT_TRUNC> 4 "register_operand" "W87,W87,W87,W87, vr, vr")] ORDER) - (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, vu, 0, 0, vu, 0")))] + (match_operand:<VINDEX_OCT_TRUNC> 4 "register_operand" " W87, W87, vr, vr")] ORDER) + (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vl<order>xei<oct_trunc_sew>.v\t%0,(%z3),%4%p1" [(set_attr "type" "vld<order>x") (set_attr "mode" "<MODE>") - (set_attr "group_overlap" "W87,W87,W87,W87,none,none")]) + (set_attr "group_overlap" "W87,W87,none,none")]) ;; DEST eew is smaller than SOURCE eew. (define_insn "@pred_indexed_<order>load<mode>_x2_smaller_eew" @@ -3733,66 +3733,66 @@ ;; Vector Double-Widening Sign-extend and Zero-extend. (define_insn "@pred_<optab><mode>_vf2" - [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") (if_then_else:VWEXTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_extend:VWEXTI - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "v<sz>ext.vf2\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "<MODE>") - (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) ;; Vector Quad-Widening Sign-extend and Zero-extend. (define_insn "@pred_<optab><mode>_vf4" - [(set (match_operand:VQEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VQEXTI 0 "register_operand" "=vr, vr, vr, vr, ?&vr, ?&vr") (if_then_else:VQEXTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_extend:VQEXTI - (match_operand:<V_QUAD_TRUNC> 3 "register_operand" "W43,W43,W43,W43,W86,W86,W86,W86, vr, vr")) - (match_operand:VQEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand:<V_QUAD_TRUNC> 3 "register_operand" " W43, W43, W86, W86, vr, vr")) + (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "v<sz>ext.vf4\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "<MODE>") - (set_attr "group_overlap" "W43,W43,W43,W43,W86,W86,W86,W86,none,none")]) + (set_attr "group_overlap" "W43,W43,W86,W86,none,none")]) ;; Vector Oct-Widening Sign-extend and Zero-extend. (define_insn "@pred_<optab><mode>_vf8" - [(set (match_operand:VOEXTI 0 "register_operand" "=vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VOEXTI 0 "register_operand" "=vr, vr, ?&vr, ?&vr") (if_then_else:VOEXTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_extend:VOEXTI - (match_operand:<V_OCT_TRUNC> 3 "register_operand" "W87,W87,W87,W87, vr, vr")) - (match_operand:VOEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, 0")))] + (match_operand:<V_OCT_TRUNC> 3 "register_operand" " W87, W87, vr, vr")) + (match_operand:VOEXTI 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "v<sz>ext.vf8\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "<MODE>") - (set_attr "group_overlap" "W87,W87,W87,W87,none,none")]) + (set_attr "group_overlap" "W87,W87,none,none")]) ;; Vector Widening Add/Subtract/Multiply. (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>" @@ -3818,28 +3818,28 @@ (set_attr "mode" "<V_DOUBLE_TRUNC>")]) (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") (if_then_else:VWEXTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_widen_binop:VWEXTI (any_extend:VWEXTI - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")) + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) (any_extend:VWEXTI (vec_duplicate:<V_DOUBLE_TRUNC> - (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")))) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")))) + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vw<any_widen_binop:insn><any_extend:u>.vx\t%0,%3,%z4%p1" [(set_attr "type" "vi<widen_binop_insn_type>") (set_attr "mode" "<V_DOUBLE_TRUNC>") - (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) (define_insn "@pred_single_widen_sub<any_extend:su><mode>" [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr") @@ -3928,47 +3928,47 @@ (set_attr "mode" "<V_DOUBLE_TRUNC>")]) (define_insn "@pred_widen_mulsu<mode>_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") (if_then_else:VWEXTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (mult:VWEXTI (sign_extend:VWEXTI - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")) + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) (zero_extend:VWEXTI (vec_duplicate:<V_DOUBLE_TRUNC> - (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")))) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")))) + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vwmulsu.vx\t%0,%3,%z4%p1" [(set_attr "type" "viwmul") (set_attr "mode" "<V_DOUBLE_TRUNC>") - (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) ;; vwcvt<u>.x.x.v (define_insn "@pred_<optab><mode>" - [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") (if_then_else:VWEXTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (any_extend:VWEXTI - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")) + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) (vec_duplicate:VWEXTI (reg:<VEL> X0_REGNUM))) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vwcvt<u>.x.x.v\t%0,%3%p1" [(set_attr "type" "viwalu") @@ -3977,7 +3977,7 @@ (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) (set (attr "avl_type_idx") (const_int 7)) - (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated integer Narrowing operations @@ -7113,32 +7113,32 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_dual_widen_<optab><mode>_scalar" - [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") (if_then_else:VWEXTF (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 9 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_widen_binop:VWEXTF (float_extend:VWEXTF - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")) + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) (float_extend:VWEXTF (vec_duplicate:<V_DOUBLE_TRUNC> - (match_operand:<VSUBEL> 4 "register_operand" " f, f, f, f, f, f, f, f, f, f, f, f, f, f")))) - (match_operand:VWEXTF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand:<VSUBEL> 4 "register_operand" " f, f, f, f, f, f, f, f")))) + (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vfw<insn>.vf\t%0,%3,%4%p1" [(set_attr "type" "vf<widen_binop_insn_type>") (set_attr "mode" "<V_DOUBLE_TRUNC>") (set (attr "frm_mode") (symbol_ref "riscv_vector::get_frm_mode (operands[9])")) - (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) (define_insn "@pred_single_widen_add<mode>" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") @@ -7709,88 +7709,88 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>" - [(set (match_operand:VWCONVERTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VWCONVERTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") (if_then_else:VWCONVERTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (unspec:VWCONVERTI - [(match_operand:<VNCONVERT> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")] VFCVTS) - (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + [(match_operand:<VNCONVERT> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")] VFCVTS) + (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vfwcvt.x<v_su>.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi") (set_attr "mode" "<VNCONVERT>") (set (attr "frm_mode") (symbol_ref "riscv_vector::get_frm_mode (operands[8])")) - (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) (define_insn "@pred_widen_<fix_cvt><mode>" - [(set (match_operand:VWCONVERTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VWCONVERTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") (if_then_else:VWCONVERTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:VWCONVERTI - (match_operand:<VNCONVERT> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")) - (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand:<VNCONVERT> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) + (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi") (set_attr "mode" "<VNCONVERT>") - (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) (define_insn "@pred_widen_<float_cvt><mode>" - [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:V_VLSF 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") (if_then_else:V_VLSF (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_float:V_VLSF - (match_operand:<VNCONVERT> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")) - (match_operand:V_VLSF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand:<VNCONVERT> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vfwcvt.f.x<u>.v\t%0,%3%p1" [(set_attr "type" "vfwcvtitof") (set_attr "mode" "<VNCONVERT>") - (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) (define_insn "@pred_extend<mode>" - [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") (if_then_else:VWEXTF_ZVFHMIN (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (float_extend:VWEXTF_ZVFHMIN - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")) - (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) + (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vfwcvt.f.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftof") (set_attr "mode" "<V_DOUBLE_TRUNC>") - (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point narrow conversions diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c deleted file mode 100644 index 80ea65b85ff..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c +++ /dev/null @@ -1,101 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, - size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9, - size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14, - size_t sum15) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9 - + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vuint8m1_t v0 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v1 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v2 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v3 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v4 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v5 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v6 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v7 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v8 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v9 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v10 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v11 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v12 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v13 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v14 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - vuint8m1_t v15 = __riscv_vle8_v_u8m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m2_t vw0 = __riscv_vluxei8_v_i16m2 ((void *) it, v0, vl); - vint16m2_t vw1 = __riscv_vluxei8_v_i16m2 ((void *) it, v1, vl); - vint16m2_t vw2 = __riscv_vluxei8_v_i16m2 ((void *) it, v2, vl); - vint16m2_t vw3 = __riscv_vluxei8_v_i16m2 ((void *) it, v3, vl); - vint16m2_t vw4 = __riscv_vluxei8_v_i16m2 ((void *) it, v4, vl); - vint16m2_t vw5 = __riscv_vluxei8_v_i16m2 ((void *) it, v5, vl); - vint16m2_t vw6 = __riscv_vluxei8_v_i16m2 ((void *) it, v6, vl); - vint16m2_t vw7 = __riscv_vluxei8_v_i16m2 ((void *) it, v7, vl); - vint16m2_t vw8 = __riscv_vluxei8_v_i16m2 ((void *) it, v8, vl); - vint16m2_t vw9 = __riscv_vluxei8_v_i16m2 ((void *) it, v9, vl); - vint16m2_t vw10 = __riscv_vluxei8_v_i16m2 ((void *) it, v10, vl); - vint16m2_t vw11 = __riscv_vluxei8_v_i16m2 ((void *) it, v11, vl); - vint16m2_t vw12 = __riscv_vluxei8_v_i16m2 ((void *) it, v12, vl); - vint16m2_t vw13 = __riscv_vluxei8_v_i16m2 ((void *) it, v13, vl); - vint16m2_t vw14 = __riscv_vluxei8_v_i16m2 ((void *) it, v14, vl); - vbool8_t mask = *(vbool8_t*)it; - vint16m2_t vw15 = __riscv_vluxei8_v_i16m2_m (mask, (void *) it, v15, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3); - size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4); - size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5); - size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6); - size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7); - size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8); - size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9); - size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10); - size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11); - size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12); - size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13); - size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14); - size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8, - sum9, sum10, sum11, sum12, sum13, sum14, sum15); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vluxei8\.v\tv0,\s*\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} } } */