Hi!
On 12/17/21 11:36 AM, Segher Boessenkool wrote:
> The builtins now all return "long". The patterns have :GPR as the
> output mode, so they can be 32-bit as well (the instruction makes sense
> in 32 bit just fine). The builtins expand to the DImode version
> normally, but to the SImode if {32bit} is true.
>
> 2021-12-17 Segher Boessenkool <seg...@kernel.crashing.org>
>
> PR target/103624
> * config/rs6000/rs6000-builtins.def (__builtin_darn): Expand to
> darn_64_di. Add {32bit} attribute. Return long.
> (__builtin_darn_32): Expand to darn_32_di. Add {32bit} attribute.
> Return long.
> (__builtin_darn_raw): Expand to darn_raw_di. Add {32bit} attribute.
> Return long.
> * config/rs6000/rs6000-call.c (rs6000_expand_builtin): Expand the darn
> builtins to the _si variants for -m32.
> * config/rs6000/rs6000.md (UNSPECV_DARN_32, UNSPECV_DARN_RAW): Delete.
> (UNSPECV_DARN): Update comment.
> (darn_32, darn_raw, darn): Delete.
> (darn_32_<mode>, darn_64_<mode>, darn_raw_<mode> for GPR): New.
> (@darn<mode> for GPR): New.
Patch LGTM. Thanks for doing the legwork on this!
Bill
>
> ---
> gcc/config/rs6000/rs6000-builtins.def | 12 ++++-----
> gcc/config/rs6000/rs6000-call.c | 6 +++++
> gcc/config/rs6000/rs6000.md | 47
> +++++++++++++++++++++--------------
> 3 files changed, 40 insertions(+), 25 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000-builtins.def
> b/gcc/config/rs6000/rs6000-builtins.def
> index 45ce160bd421..3ad5a135eaec 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -2798,14 +2798,14 @@
>
> ; Miscellaneous P9 functions
> [power9]
> - signed long long __builtin_darn ();
> - DARN darn {}
> + signed long __builtin_darn ();
> + DARN darn_64_di {32bit}
>
> - signed int __builtin_darn_32 ();
> - DARN_32 darn_32 {}
> + signed long __builtin_darn_32 ();
> + DARN_32 darn_32_di {32bit}
>
> - signed long long __builtin_darn_raw ();
> - DARN_RAW darn_raw {}
> + signed long __builtin_darn_raw ();
> + DARN_RAW darn_raw_di {32bit}
>
> const signed int __builtin_dtstsfi_eq_dd (const int<6>, _Decimal64);
> TSTSFI_EQ_DD dfptstsfi_eq_dd {}
> diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
> index b98f4a4c97f7..cc55174c6b72 100644
> --- a/gcc/config/rs6000/rs6000-call.c
> +++ b/gcc/config/rs6000/rs6000-call.c
> @@ -5631,6 +5631,12 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
> subtarget */,
> icode = CODE_FOR_rs6000_mftb_si;
> else if (fcode == RS6000_BIF_BPERMD)
> icode = CODE_FOR_bpermd_si;
> + else if (fcode == RS6000_BIF_DARN)
> + icode = CODE_FOR_darn_64_si;
> + else if (fcode == RS6000_BIF_DARN_32)
> + icode = CODE_FOR_darn_32_si;
> + else if (fcode == RS6000_BIF_DARN_RAW)
> + icode = CODE_FOR_darn_raw_si;
> else
> gcc_unreachable ();
> }
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 4122acb98cfd..9be484c7cf83 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -172,9 +172,7 @@ (define_c_enum "unspecv"
> UNSPECV_EH_RR ; eh_reg_restore
> UNSPECV_ISYNC ; isync instruction
> UNSPECV_MFTB ; move from time base
> - UNSPECV_DARN ; darn 1 (deliver a random number)
> - UNSPECV_DARN_32 ; darn 2
> - UNSPECV_DARN_RAW ; darn 0
> + UNSPECV_DARN ; darn (deliver a random number)
> UNSPECV_NLGR ; non-local goto receiver
> UNSPECV_MFFS ; Move from FPSCR
> UNSPECV_MFFSL ; Move from FPSCR light instruction version
> @@ -15065,25 +15063,36 @@ (define_insn "*cmp<mode>_hw"
>
> ;; Miscellaneous ISA 3.0 (power9) instructions
>
> -(define_insn "darn_32"
> - [(set (match_operand:SI 0 "register_operand" "=r")
> - (unspec_volatile:SI [(const_int 0)] UNSPECV_DARN_32))]
> +(define_expand "darn_32_<mode>"
> + [(use (match_operand:GPR 0 "register_operand"))]
> "TARGET_P9_MISC"
> - "darn %0,0"
> - [(set_attr "type" "integer")])
> +{
> + emit_insn (gen_darn (<MODE>mode, operands[0], const0_rtx));
> + DONE;
> +})
>
> -(define_insn "darn_raw"
> - [(set (match_operand:DI 0 "register_operand" "=r")
> - (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN_RAW))]
> - "TARGET_P9_MISC && TARGET_64BIT"
> - "darn %0,2"
> - [(set_attr "type" "integer")])
> +(define_expand "darn_64_<mode>"
> + [(use (match_operand:GPR 0 "register_operand"))]
> + "TARGET_P9_MISC"
> +{
> + emit_insn (gen_darn (<MODE>mode, operands[0], const1_rtx));
> + DONE;
> +})
>
> -(define_insn "darn"
> - [(set (match_operand:DI 0 "register_operand" "=r")
> - (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN))]
> - "TARGET_P9_MISC && TARGET_64BIT"
> - "darn %0,1"
> +(define_expand "darn_raw_<mode>"
> + [(use (match_operand:GPR 0 "register_operand"))]
> + "TARGET_P9_MISC"
> +{
> + emit_insn (gen_darn (<MODE>mode, operands[0], const2_rtx));
> + DONE;
> +})
> +
> +(define_insn "@darn<mode>"
> + [(set (match_operand:GPR 0 "register_operand" "=r")
> + (unspec_volatile:GPR [(match_operand 1 "const_int_operand" "n")]
> + UNSPECV_DARN))]
> + "TARGET_P9_MISC"
> + "darn %0,%1"
> [(set_attr "type" "integer")])
>
> ;; Test byte within range.
