This patch fixes PR middle-end/80270, an ICE-on-valid regression, where performing a bitfield extraction on a variable explicitly stored in a hard register by the user causes a segmentation fault during RTL expansion. Nearly identical source code without the "asm" qualifier compiles fine. The point of divergence is in simplify_gen_subreg which tries to avoid creating non-trivial SUBREGs of hard registers, to avoid problems during register allocation. This suggests the simple solution proposed here, to copy hard registers to a new pseudo in extract_integral_bit_field, just before calling simplify_gen_subreg.
This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check with no new failures. Ok for mainline? 2022-02-27 Roger Sayle <ro...@nextmovesoftware.com> gcc/ChangeLog PR middle-end/80270 * expmed.cc (extract_integral_bit_field): If OP0 is a hard register, copy it to a pseudo before calling simplify_gen_subreg. gcc/testsuite/ChangeLog * gcc.target/i386/pr80270.c: New test case. Thanks in advance, Roger --
diff --git a/gcc/expmed.cc b/gcc/expmed.cc index 80a16ce..b51450d 100644 --- a/gcc/expmed.cc +++ b/gcc/expmed.cc @@ -1975,6 +1975,14 @@ extract_integral_bit_field (rtx op0, opt_scalar_int_mode op0_mode, unsignedp, reverse); return convert_extracted_bit_field (target, mode, tmode, unsignedp); } + /* If OP0 is a hard register, copy it to a pseudo before calling + simplify_gen_subreg. */ + if (REG_P (op0) && HARD_REGISTER_P (op0)) + { + rtx tmp = gen_reg_rtx (GET_MODE (op0)); + emit_move_insn (tmp, op0); + op0 = tmp; + } op0 = simplify_gen_subreg (word_mode, op0, op0_mode.require (), bitnum / BITS_PER_WORD * UNITS_PER_WORD); op0_mode = word_mode; diff --git a/gcc/testsuite/gcc.target/i386/pr80270.c b/gcc/testsuite/gcc.target/i386/pr80270.c new file mode 100644 index 0000000..89e9c33 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr80270.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse" } */ + +typedef int v8 __attribute__((vector_size(8))); +struct S1 { + v8 s1f; +}; +struct S2 { + struct S1 s2f1; + v8 s2f2; +}; + +extern void foo(int); + +void bar() { + int tmp, i = 3; + register struct S2 b asm("xmm0"); + tmp = b.s2f1.s1f[i]; + foo(tmp); +} +