From: Christoph Müllner <christoph.muell...@vrull.eu> This series adds support for the following vendor extensions from T-Head:
* XTheadCmo, XTheadSync * XTheadBa, XTheadBb, XTheadBs * XTheadCondMov * XTheadMac * XTheadFmv, XTheadInt No regressions observed. Christoph Müllner (7): riscv: Add basic XThead* vendor extension support riscv: riscv-cores.def: Add T-Head XuanTie C906 riscv: thead: Add support for XTheadBa and XTheadBs ISA extensions riscv: thead: Add support for XTheadCondMov ISA extensions riscv: thead: Add support for XTheadBb ISA extension riscv: thead: Add support for XTheadMac ISA extension riscv: Add basic extension support for XTheadFmv and XTheadInt gcc/common/config/riscv/riscv-common.cc | 24 ++ gcc/config/riscv/bitmanip.md | 47 +++- gcc/config/riscv/iterators.md | 4 + gcc/config/riscv/riscv-cores.def | 2 + gcc/config/riscv/riscv-opts.h | 23 ++ gcc/config/riscv/riscv.cc | 67 ++++- gcc/config/riscv/riscv.md | 52 +++- gcc/config/riscv/riscv.opt | 3 + gcc/config/riscv/thead.md | 252 ++++++++++++++++++ .../gcc.target/riscv/mcpu-thead-c906.c | 18 ++ gcc/testsuite/gcc.target/riscv/thead-mula-1.c | 40 +++ gcc/testsuite/gcc.target/riscv/thead-mula-2.c | 28 ++ .../gcc.target/riscv/xtheadba-addsl-64.c | 18 ++ .../gcc.target/riscv/xtheadba-addsl.c | 20 ++ gcc/testsuite/gcc.target/riscv/xtheadba.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 19 ++ .../gcc.target/riscv/xtheadbb-extu.c | 12 + gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 40 +++ .../gcc.target/riscv/xtheadbb-srri.c | 18 ++ gcc/testsuite/gcc.target/riscv/xtheadbb.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 12 + gcc/testsuite/gcc.target/riscv/xtheadbs.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 13 + .../riscv/xtheadcondmov-mveqz-imm-eqz.c | 37 +++ .../riscv/xtheadcondmov-mveqz-imm-not.c | 37 +++ .../riscv/xtheadcondmov-mveqz-reg-eqz.c | 37 +++ .../riscv/xtheadcondmov-mveqz-reg-not.c | 37 +++ .../riscv/xtheadcondmov-mvnez-imm-cond.c | 37 +++ .../riscv/xtheadcondmov-mvnez-imm-nez.c | 37 +++ .../riscv/xtheadcondmov-mvnez-reg-cond.c | 37 +++ .../riscv/xtheadcondmov-mvnez-reg-nez.c | 37 +++ .../gcc.target/riscv/xtheadcondmov.c | 13 + .../gcc.target/riscv/xtheadfmemidx.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadmac.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadsync.c | 13 + 38 files changed, 1123 insertions(+), 17 deletions(-) create mode 100644 gcc/config/riscv/thead.md create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c create mode 100644 gcc/testsuite/gcc.target/riscv/thead-mula-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/thead-mula-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl-64.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c -- 2.38.1