> On Fri, 23 Dec 2022, Qing Zhao wrote: >> >> I am a little confused, you mean pre-RA scheduler does not look at the >> >> data flow >> >> information at all when scheduling insns across calls currently? >> > >> > I think it does not inspect liveness info, and may extend lifetime of a >> > pseudo >> > across a call, transforming >> > >> > call foo >> > reg = 1 >> > ... >> > use reg >> > >> > to >> > >> > reg = 1 >> > call foo >> > ... >> > use reg >> > >> > but this is undesirable, because now register allocation cannot select a >> > call-clobbered register for 'reg’. >> Okay, thanks for the explanation. >> >> Then, why not just check the liveness info instead of inhibiting all >> scheduling across calls? > > Because there's almost nothing to gain from pre-RA scheduling across calls in > the first place. Remember that the call transfers control flow elsewhere and > therefore the scheduler has no idea about the pipeline state after the call > and after the return, so modeling-wise it's a gamble. > > For instructions that lie on a critical path such scheduling can be useful > when > it substantially reduces the difference between the priority of the call and > nearby instructions of the critical path. But we don't track which > instructions > are on critical path(s) and which are not. > > (scheduling across calls in sched2 is somewhat dubious as well, but > it doesn't risk register pressure issues, and on VLIW CPUs it at least > can result in better VLIW packing)
Does sched2 actually schedule across calls? All the comments in the source code stress the fact that the second scheduler pass (after register allocation) works in regions that correspond to basic blocks: "(after reload, each region is of one block)".
