From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vssra_vx-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tu-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tum-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tum-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tum-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tumu-3.C: New test.
---
.../g++.target/riscv/rvv/base/vssra_vx-1.C | 314 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vssra_vx-2.C | 314 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vssra_vx-3.C | 314 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vssra_vx_mu-1.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vssra_vx_mu-2.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vssra_vx_mu-3.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vssra_vx_tu-1.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vssra_vx_tu-2.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vssra_vx_tu-3.C | 160 +++++++++
.../riscv/rvv/base/vssra_vx_tum-1.C | 160 +++++++++
.../riscv/rvv/base/vssra_vx_tum-2.C | 160 +++++++++
.../riscv/rvv/base/vssra_vx_tum-3.C | 160 +++++++++
.../riscv/rvv/base/vssra_vx_tumu-1.C | 160 +++++++++
.../riscv/rvv/base/vssra_vx_tumu-2.C | 160 +++++++++
.../riscv/rvv/base/vssra_vx_tumu-3.C | 160 +++++++++
15 files changed, 2862 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-3.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C
new file mode 100644
index 00000000000..23985cd3ebb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra(vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra(vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra(vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra(vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra(vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra(vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra(vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra(vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra(vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra(vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra(vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra(vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra(vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra(vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra(vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra(vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra(vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra(vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra(vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra(vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra(vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra(vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf8_t test___riscv_vssra(vbool64_t mask,vint8mf8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra(vbool32_t mask,vint8mf4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra(vbool16_t mask,vint8mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra(vbool8_t mask,vint8m1_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra(vbool4_t mask,vint8m2_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra(vbool2_t mask,vint8m4_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra(vbool1_t mask,vint8m8_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra(vbool64_t mask,vint16mf4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra(vbool32_t mask,vint16mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra(vbool16_t mask,vint16m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra(vbool8_t mask,vint16m2_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra(vbool4_t mask,vint16m4_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra(vbool2_t mask,vint16m8_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra(vbool64_t mask,vint32mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra(vbool32_t mask,vint32m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra(vbool16_t mask,vint32m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra(vbool8_t mask,vint32m4_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra(vbool4_t mask,vint32m8_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra(vbool64_t mask,vint64m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra(vbool32_t mask,vint64m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra(vbool16_t mask,vint64m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra(vbool8_t mask,vint64m8_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-2.C
new file mode 100644
index 00000000000..c7f36db94f8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra(vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra(vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra(vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra(vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra(vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra(vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra(vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra(vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra(vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra(vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra(vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra(vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra(vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra(vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra(vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra(vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra(vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra(vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra(vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra(vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra(vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra(vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8mf8_t test___riscv_vssra(vbool64_t mask,vint8mf8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra(vbool32_t mask,vint8mf4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra(vbool16_t mask,vint8mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra(vbool8_t mask,vint8m1_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra(vbool4_t mask,vint8m2_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra(vbool2_t mask,vint8m4_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra(vbool1_t mask,vint8m8_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra(vbool64_t mask,vint16mf4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra(vbool32_t mask,vint16mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra(vbool16_t mask,vint16m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra(vbool8_t mask,vint16m2_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra(vbool4_t mask,vint16m4_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra(vbool2_t mask,vint16m8_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra(vbool64_t mask,vint32mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra(vbool32_t mask,vint32m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra(vbool16_t mask,vint32m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra(vbool8_t mask,vint32m4_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra(vbool4_t mask,vint32m8_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra(vbool64_t mask,vint64m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra(vbool32_t mask,vint64m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra(vbool16_t mask,vint64m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra(vbool8_t mask,vint64m8_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-3.C
new file mode 100644
index 00000000000..c5ff47ae379
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra(vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra(vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra(vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra(vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra(vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra(vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra(vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra(vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra(vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra(vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra(vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra(vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra(vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra(vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra(vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra(vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra(vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra(vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra(vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra(vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra(vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra(vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8mf8_t test___riscv_vssra(vbool64_t mask,vint8mf8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra(vbool32_t mask,vint8mf4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra(vbool16_t mask,vint8mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra(vbool8_t mask,vint8m1_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra(vbool4_t mask,vint8m2_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra(vbool2_t mask,vint8m4_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra(vbool1_t mask,vint8m8_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra(vbool64_t mask,vint16mf4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra(vbool32_t mask,vint16mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra(vbool16_t mask,vint16m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra(vbool8_t mask,vint16m2_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra(vbool4_t mask,vint16m4_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra(vbool2_t mask,vint16m8_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra(vbool64_t mask,vint32mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra(vbool32_t mask,vint32m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra(vbool16_t mask,vint32m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra(vbool8_t mask,vint32m4_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra(vbool4_t mask,vint32m8_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra(vbool64_t mask,vint64m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra(vbool32_t mask,vint64m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra(vbool16_t mask,vint64m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra(vbool8_t mask,vint64m8_t op1,size_t shift,size_t
vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-1.C
new file mode 100644
index 00000000000..2490257db8b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-2.C
new file mode 100644
index 00000000000..a335a9591ed
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-3.C
new file mode 100644
index 00000000000..2e70517cade
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-1.C
new file mode 100644
index 00000000000..4b52410c216
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tu(vint8mf8_t merge,vint8mf8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_tu(vint8mf4_t merge,vint8mf4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_tu(vint8mf2_t merge,vint8mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_tu(vint8m1_t merge,vint8m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_tu(vint8m2_t merge,vint8m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_tu(vint8m4_t merge,vint8m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_tu(vint8m8_t merge,vint8m8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_tu(vint16mf4_t merge,vint16mf4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_tu(vint16mf2_t merge,vint16mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_tu(vint16m1_t merge,vint16m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_tu(vint16m2_t merge,vint16m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_tu(vint16m4_t merge,vint16m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_tu(vint16m8_t merge,vint16m8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_tu(vint32mf2_t merge,vint32mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_tu(vint32m1_t merge,vint32m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_tu(vint32m2_t merge,vint32m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_tu(vint32m4_t merge,vint32m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_tu(vint32m8_t merge,vint32m8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_tu(vint64m1_t merge,vint64m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_tu(vint64m2_t merge,vint64m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_tu(vint64m4_t merge,vint64m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_tu(vint64m8_t merge,vint64m8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-2.C
new file mode 100644
index 00000000000..63076738b1f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tu(vint8mf8_t merge,vint8mf8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_tu(vint8mf4_t merge,vint8mf4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_tu(vint8mf2_t merge,vint8mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_tu(vint8m1_t merge,vint8m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_tu(vint8m2_t merge,vint8m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_tu(vint8m4_t merge,vint8m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_tu(vint8m8_t merge,vint8m8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_tu(vint16mf4_t merge,vint16mf4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_tu(vint16mf2_t merge,vint16mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_tu(vint16m1_t merge,vint16m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_tu(vint16m2_t merge,vint16m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_tu(vint16m4_t merge,vint16m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_tu(vint16m8_t merge,vint16m8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_tu(vint32mf2_t merge,vint32mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_tu(vint32m1_t merge,vint32m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_tu(vint32m2_t merge,vint32m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_tu(vint32m4_t merge,vint32m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_tu(vint32m8_t merge,vint32m8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_tu(vint64m1_t merge,vint64m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_tu(vint64m2_t merge,vint64m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_tu(vint64m4_t merge,vint64m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_tu(vint64m8_t merge,vint64m8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-3.C
new file mode 100644
index 00000000000..111e3a06084
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tu(vint8mf8_t merge,vint8mf8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_tu(vint8mf4_t merge,vint8mf4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_tu(vint8mf2_t merge,vint8mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_tu(vint8m1_t merge,vint8m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_tu(vint8m2_t merge,vint8m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_tu(vint8m4_t merge,vint8m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_tu(vint8m8_t merge,vint8m8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_tu(vint16mf4_t merge,vint16mf4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_tu(vint16mf2_t merge,vint16mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_tu(vint16m1_t merge,vint16m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_tu(vint16m2_t merge,vint16m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_tu(vint16m4_t merge,vint16m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_tu(vint16m8_t merge,vint16m8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_tu(vint32mf2_t merge,vint32mf2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_tu(vint32m1_t merge,vint32m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_tu(vint32m2_t merge,vint32m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_tu(vint32m4_t merge,vint32m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_tu(vint32m8_t merge,vint32m8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_tu(vint64m1_t merge,vint64m1_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_tu(vint64m2_t merge,vint64m2_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_tu(vint64m4_t merge,vint64m4_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_tu(vint64m8_t merge,vint64m8_t op1,size_t
shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-1.C
new file mode 100644
index 00000000000..b015812d2c6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_tum(vbool64_t mask,vint16mf4_t
merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_tum(vbool32_t mask,vint16mf2_t
merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_tum(vbool64_t mask,vint32mf2_t
merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-2.C
new file mode 100644
index 00000000000..80247efaf83
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_tum(vbool64_t mask,vint16mf4_t
merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_tum(vbool32_t mask,vint16mf2_t
merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_tum(vbool64_t mask,vint32mf2_t
merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-3.C
new file mode 100644
index 00000000000..50f075811ae
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_tum(vbool64_t mask,vint16mf4_t
merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_tum(vbool32_t mask,vint16mf2_t
merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_tum(vbool64_t mask,vint32mf2_t
merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-1.C
new file mode 100644
index 00000000000..632fb380f59
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_tumu(vbool64_t mask,vint16mf4_t
merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_tumu(vbool32_t mask,vint16mf2_t
merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_tumu(vbool64_t mask,vint32mf2_t
merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-2.C
new file mode 100644
index 00000000000..1249c6cfd8f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_tumu(vbool64_t mask,vint16mf4_t
merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_tumu(vbool32_t mask,vint16mf2_t
merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_tumu(vbool64_t mask,vint32mf2_t
merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-3.C
new file mode 100644
index 00000000000..90cb29e8e4e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_tumu(vbool64_t mask,vint16mf4_t
merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_tumu(vbool32_t mask,vint16mf2_t
merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_tumu(vbool64_t mask,vint32mf2_t
merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+}
1 } } */
--
2.36.3
