(Pinging since I realised that this is required for my later Low Overhead Loop
patch series to work)
Ok for trunk with the updated changelog that Christophe mentioned?
Thanks,
Stamatis/Stam Markianos-Wright
________________________________
From: Stam Markianos-Wright
Sent: Tuesday, August 1, 2023 6:21 PM
To: gcc-patches@gcc.gnu.org <gcc-patches@gcc.gnu.org>
Cc: Richard Earnshaw <richard.earns...@arm.com>; Kyrylo Tkachov
<kyrylo.tkac...@arm.com>
Subject: arm: Remove unsigned variant of vcaddq_m
Hi all,
The unsigned variants of the vcaddq_m operation are not needed within the
compiler, as the assembly output of the signed and unsigned versions of the
ops is identical: with a `.i` suffix (as opposed to separate `.s` and `.u`
suffixes).
Tested with baremetal arm-none-eabi on Arm's fastmodels.
Ok for trunk?
Thanks,
Stamatis Markianos-Wright
gcc/ChangeLog:
* config/arm/arm-mve-builtins-base.cc (vcaddq_rot90, vcaddq_rot270):
Use common insn for signed and unsigned front-end definitions.
* config/arm/arm_mve_builtins.def
(vcaddq_rot90_m_u, vcaddq_rot270_m_u): Make common.
(vcaddq_rot90_m_s, vcaddq_rot270_m_s): Remove.
* config/arm/iterators.md (mve_insn): Merge signed and unsigned defs.
(isu): Likewise.
(rot): Likewise.
(mve_rot): Likewise.
(supf): Likewise.
(VxCADDQ_M): Likewise.
* config/arm/unspecs.md (unspec): Likewise.
---
gcc/config/arm/arm-mve-builtins-base.cc | 4 ++--
gcc/config/arm/arm_mve_builtins.def | 6 ++---
gcc/config/arm/iterators.md | 30 +++++++++++--------------
gcc/config/arm/mve.md | 4 ++--
gcc/config/arm/unspecs.md | 6 ++---
5 files changed, 21 insertions(+), 29 deletions(-)
diff --git a/gcc/config/arm/arm-mve-builtins-base.cc
b/gcc/config/arm/arm-mve-builtins-base.cc
index e31095ae112..426a87e9852 100644
--- a/gcc/config/arm/arm-mve-builtins-base.cc
+++ b/gcc/config/arm/arm-mve-builtins-base.cc
@@ -260,8 +260,8 @@ FUNCTION_PRED_P_S_U (vaddvq, VADDVQ)
FUNCTION_PRED_P_S_U (vaddvaq, VADDVAQ)
FUNCTION_WITH_RTX_M (vandq, AND, VANDQ)
FUNCTION_ONLY_N (vbrsrq, VBRSRQ)
-FUNCTION (vcaddq_rot90, unspec_mve_function_exact_insn_rot,
(UNSPEC_VCADD90, UNSPEC_VCADD90, UNSPEC_VCADD90, VCADDQ_ROT90_M_S,
VCADDQ_ROT90_M_U, VCADDQ_ROT90_M_F))
-FUNCTION (vcaddq_rot270, unspec_mve_function_exact_insn_rot,
(UNSPEC_VCADD270, UNSPEC_VCADD270, UNSPEC_VCADD270, VCADDQ_ROT270_M_S,
VCADDQ_ROT270_M_U, VCADDQ_ROT270_M_F))
+FUNCTION (vcaddq_rot90, unspec_mve_function_exact_insn_rot,
(UNSPEC_VCADD90, UNSPEC_VCADD90, UNSPEC_VCADD90, VCADDQ_ROT90_M,
VCADDQ_ROT90_M, VCADDQ_ROT90_M_F))
+FUNCTION (vcaddq_rot270, unspec_mve_function_exact_insn_rot,
(UNSPEC_VCADD270, UNSPEC_VCADD270, UNSPEC_VCADD270, VCADDQ_ROT270_M,
VCADDQ_ROT270_M, VCADDQ_ROT270_M_F))
FUNCTION (vcmlaq, unspec_mve_function_exact_insn_rot, (-1, -1,
UNSPEC_VCMLA, -1, -1, VCMLAQ_M_F))
FUNCTION (vcmlaq_rot90, unspec_mve_function_exact_insn_rot, (-1, -1,
UNSPEC_VCMLA90, -1, -1, VCMLAQ_ROT90_M_F))
FUNCTION (vcmlaq_rot180, unspec_mve_function_exact_insn_rot, (-1, -1,
UNSPEC_VCMLA180, -1, -1, VCMLAQ_ROT180_M_F))
diff --git a/gcc/config/arm/arm_mve_builtins.def
b/gcc/config/arm/arm_mve_builtins.def
index 43dacc3dda1..6ac1812c697 100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -523,8 +523,8 @@ VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED,
vhsubq_m_n_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhaddq_m_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhaddq_m_n_u, v16qi, v8hi,
v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, veorq_m_u, v16qi, v8hi, v4si)
-VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vcaddq_rot90_m_u, v16qi,
v8hi, v4si)
-VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vcaddq_rot270_m_u, v16qi,
v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vcaddq_rot90_m_, v16qi,
v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vcaddq_rot270_m_, v16qi,
v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vbicq_m_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vandq_m_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vaddq_m_u, v16qi, v8hi, v4si)
@@ -587,8 +587,6 @@ VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED,
vhcaddq_rot270_m_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhaddq_m_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhaddq_m_n_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, veorq_m_s, v16qi, v8hi, v4si)
-VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcaddq_rot90_m_s, v16qi, v8hi, v4si)
-VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcaddq_rot270_m_s, v16qi, v8hi,
v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbrsrq_m_n_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbicq_m_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vandq_m_s, v16qi, v8hi, v4si)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index b13ff53d36f..2edd0b06370 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -941,8 +941,8 @@
(VBICQ_N_S "vbic") (VBICQ_N_U "vbic")
(VBRSRQ_M_N_S "vbrsr") (VBRSRQ_M_N_U "vbrsr") (VBRSRQ_M_N_F
"vbrsr")
(VBRSRQ_N_S "vbrsr") (VBRSRQ_N_U "vbrsr") (VBRSRQ_N_F "vbrsr")
- (VCADDQ_ROT270_M_U "vcadd") (VCADDQ_ROT270_M_S "vcadd")
(VCADDQ_ROT270_M_F "vcadd")
- (VCADDQ_ROT90_M_U "vcadd") (VCADDQ_ROT90_M_S "vcadd")
(VCADDQ_ROT90_M_F "vcadd")
+ (VCADDQ_ROT270_M "vcadd") (VCADDQ_ROT270_M_F "vcadd")
+ (VCADDQ_ROT90_M "vcadd") (VCADDQ_ROT90_M_F "vcadd")
(VCLSQ_M_S "vcls")
(VCLSQ_S "vcls")
(VCLZQ_M_S "vclz") (VCLZQ_M_U "vclz")
@@ -1215,8 +1215,8 @@
(define_int_attr isu [
(UNSPEC_VCADD90 "i") (UNSPEC_VCADD270 "i")
(VABSQ_M_S "s")
- (VCADDQ_ROT270_M_U "i") (VCADDQ_ROT270_M_S "i")
- (VCADDQ_ROT90_M_U "i") (VCADDQ_ROT90_M_S "i")
+ (VCADDQ_ROT270_M "i")
+ (VCADDQ_ROT90_M "i")
(VCLSQ_M_S "s")
(VCLZQ_M_S "i")
(VCLZQ_M_U "i")
@@ -2184,11 +2184,9 @@
(define_int_attr rot [(UNSPEC_VCADD90 "90")
(UNSPEC_VCADD270 "270")
(VCADDQ_ROT90_M_F "90")
- (VCADDQ_ROT90_M_S "90")
- (VCADDQ_ROT90_M_U "90")
+ (VCADDQ_ROT90_M "90")
(VCADDQ_ROT270_M_F "270")
- (VCADDQ_ROT270_M_S "270")
- (VCADDQ_ROT270_M_U "270")
+ (VCADDQ_ROT270_M "270")
(VHCADDQ_ROT90_S "90")
(VHCADDQ_ROT270_S "270")
(VHCADDQ_ROT90_M_S "90")
@@ -2241,11 +2239,9 @@
(define_int_attr mve_rot [(UNSPEC_VCADD90 "_rot90")
(UNSPEC_VCADD270 "_rot270")
(VCADDQ_ROT90_M_F "_rot90")
- (VCADDQ_ROT90_M_S "_rot90")
- (VCADDQ_ROT90_M_U "_rot90")
+ (VCADDQ_ROT90_M "_rot90")
(VCADDQ_ROT270_M_F "_rot270")
- (VCADDQ_ROT270_M_S "_rot270")
- (VCADDQ_ROT270_M_U "_rot270")
+ (VCADDQ_ROT270_M "_rot270")
(VHCADDQ_ROT90_S "_rot90")
(VHCADDQ_ROT270_S "_rot270")
(VHCADDQ_ROT90_M_S "_rot90")
@@ -2403,7 +2399,7 @@
(VCVTQ_M_N_TO_F_U "u") (VADDQ_M_N_U "u")
(VSHLQ_M_N_S "s") (VMAXQ_M_U "u") (VHSUBQ_M_N_U "u")
(VMULQ_M_N_S "s") (VQSHLQ_M_U "u") (VRHADDQ_M_S "s")
- (VEORQ_M_U "u") (VSHRQ_M_N_U "u") (VCADDQ_ROT90_M_U "u")
+ (VEORQ_M_U "u") (VSHRQ_M_N_U "u")
(VMLADAVAQ_P_U "u") (VEORQ_M_S "s") (VBRSRQ_M_N_S "s")
(VMULQ_M_U "u") (VQRDMLAHQ_M_N_S "s") (VHSUBQ_M_N_S "s")
(VQRSHLQ_M_S "s") (VMULQ_M_N_U "u")
@@ -2412,17 +2408,17 @@
(VMULLBQ_INT_M_U "u") (VSHLQ_M_N_U "u") (VQSUBQ_M_U "u")
(VQDMLASHQ_M_N_S "s")
(VQRDMLASHQ_M_N_U "u") (VRSHRQ_M_N_S "s")
- (VORNQ_M_S "s") (VCADDQ_ROT270_M_S "s") (VRHADDQ_M_U "u")
+ (VORNQ_M_S "s") (VCADDQ_ROT270_M "") (VRHADDQ_M_U "u")
(VRSHRQ_M_N_U "u") (VMLASQ_M_N_U "u") (VHSUBQ_M_U "u")
(VQSUBQ_M_N_S "s") (VMULLTQ_INT_M_S "s")
(VORRQ_M_S "s") (VQDMLAHQ_M_N_U "u") (VRSHLQ_M_S "s")
(VHADDQ_M_U "u") (VHADDQ_M_N_S "s") (VMULLTQ_INT_M_U "u")
(VORRQ_M_U "u") (VHADDQ_M_S "s") (VHADDQ_M_N_U "u")
(VQDMLAHQ_M_N_S "s") (VMAXQ_M_S "s") (VORNQ_M_U "u")
- (VCADDQ_ROT270_M_U "u") (VQADDQ_M_U "u")
+ (VQADDQ_M_U "u")
(VQRDMLASHQ_M_N_S "s") (VBICQ_M_U "u") (VMINQ_M_U "u")
(VSUBQ_M_N_S "s") (VMULLBQ_INT_M_S "s") (VQSUBQ_M_S "s")
- (VCADDQ_ROT90_M_S "s") (VRMULHQ_M_S "s") (VANDQ_M_U "u")
+ (VCADDQ_ROT90_M "") (VRMULHQ_M_S "s") (VANDQ_M_U "u")
(VMULHQ_M_S "s") (VADDQ_M_S "s") (VQRDMLAHQ_M_N_U "u")
(VMLASQ_M_N_S "s") (VHSUBQ_M_S "s") (VRMULHQ_M_U "u")
(VQADDQ_M_N_S "s") (VSHRQ_M_N_S "s") (VANDQ_M_S "s")
@@ -2834,7 +2830,7 @@
(define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U])
(define_int_iterator VCADDQ_M_F [VCADDQ_ROT90_M_F VCADDQ_ROT270_M_F])
(define_int_iterator VxCADDQ [UNSPEC_VCADD90 UNSPEC_VCADD270
VHCADDQ_ROT90_S VHCADDQ_ROT270_S])
-(define_int_iterator VxCADDQ_M [VHCADDQ_ROT90_M_S VHCADDQ_ROT270_M_S
VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
+(define_int_iterator VxCADDQ_M [VHCADDQ_ROT90_M_S VHCADDQ_ROT270_M_S
VCADDQ_ROT90_M VCADDQ_ROT270_M])
(define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S])
(define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S])
(define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index a2cbcff1a6f..6e4b143affa 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -839,8 +839,8 @@
])
;;
-;; [vcaddq_rot90_s, vcadd_rot90_u]
-;; [vcaddq_rot270_s, vcadd_rot270_u]
+;; [vcaddq_rot90_s, vcaddq_rot90_u]
+;; [vcaddq_rot270_s, vcaddq_rot270_u]
;; [vhcaddq_rot90_s]
;; [vhcaddq_rot270_s]
;;
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index dccda283573..6a5b1f8f623 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -995,8 +995,7 @@
VMAXQ_M_U
VQRDMLAHQ_M_N_U
VCADDQ_ROT270_M_F
- VCADDQ_ROT270_M_U
- VCADDQ_ROT270_M_S
+ VCADDQ_ROT270_M
VQRSHLQ_M_S
VMULQ_M_F
VRHADDQ_M_U
@@ -1050,8 +1049,7 @@
VSLIQ_M_N_S
VQSHLQ_M_U
VQSHLQ_M_S
- VCADDQ_ROT90_M_U
- VCADDQ_ROT90_M_S
+ VCADDQ_ROT90_M
VORNQ_M_U
VORNQ_M_S
VQSHLQ_M_N_S
--
2.34.1
From 3f08bc4da87efd399b129e91513dc4001492886f Mon Sep 17 00:00:00 2001
From: Stamatis Markianos-Wright <stam.markianos-wri...@arm.com>
Date: Tue, 1 Aug 2023 11:59:28 +0100
Subject: [PATCH 1/1] arm: Remove unsigned variant of vcaddq_m
The unsigned variants of the vcaddq_m operation are not needed within the
compiler, as the assembly output of the signed and unsigned versions of the
ops is identical: with a `.i` suffix (as opposed to separate `.s` and `.u`
suffixes).
Tested with baremetal arm-none-eabi on Arm's fastmodels.
gcc/ChangeLog:
* config/arm/arm-mve-builtins-base.cc (vcaddq_rot90, vcaddq_rot270):
Use common insn for signed and unsigned front-end definitions.
* config/arm/arm_mve_builtins.def
(vcaddq_rot90_m_u, vcaddq_rot270_m_u): Make common.
(vcaddq_rot90_m_s, vcaddq_rot270_m_s): Remove.
* config/arm/iterators.md (mve_insn): Merge signed and unsigned defs.
(isu): Likewise.
(rot): Likewise.
(mve_rot): Likewise.
(supf): Likewise.
(VxCADDQ_M): Likewise.
* config/arm/unspecs.md (unspec): Likewise.
---
gcc/config/arm/arm-mve-builtins-base.cc | 4 ++--
gcc/config/arm/arm_mve_builtins.def | 6 ++---
gcc/config/arm/iterators.md | 30 +++++++++++--------------
gcc/config/arm/mve.md | 4 ++--
gcc/config/arm/unspecs.md | 6 ++---
5 files changed, 21 insertions(+), 29 deletions(-)
diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc
index e31095ae112..426a87e9852 100644
--- a/gcc/config/arm/arm-mve-builtins-base.cc
+++ b/gcc/config/arm/arm-mve-builtins-base.cc
@@ -260,8 +260,8 @@ FUNCTION_PRED_P_S_U (vaddvq, VADDVQ)
FUNCTION_PRED_P_S_U (vaddvaq, VADDVAQ)
FUNCTION_WITH_RTX_M (vandq, AND, VANDQ)
FUNCTION_ONLY_N (vbrsrq, VBRSRQ)
-FUNCTION (vcaddq_rot90, unspec_mve_function_exact_insn_rot, (UNSPEC_VCADD90, UNSPEC_VCADD90, UNSPEC_VCADD90, VCADDQ_ROT90_M_S, VCADDQ_ROT90_M_U, VCADDQ_ROT90_M_F))
-FUNCTION (vcaddq_rot270, unspec_mve_function_exact_insn_rot, (UNSPEC_VCADD270, UNSPEC_VCADD270, UNSPEC_VCADD270, VCADDQ_ROT270_M_S, VCADDQ_ROT270_M_U, VCADDQ_ROT270_M_F))
+FUNCTION (vcaddq_rot90, unspec_mve_function_exact_insn_rot, (UNSPEC_VCADD90, UNSPEC_VCADD90, UNSPEC_VCADD90, VCADDQ_ROT90_M, VCADDQ_ROT90_M, VCADDQ_ROT90_M_F))
+FUNCTION (vcaddq_rot270, unspec_mve_function_exact_insn_rot, (UNSPEC_VCADD270, UNSPEC_VCADD270, UNSPEC_VCADD270, VCADDQ_ROT270_M, VCADDQ_ROT270_M, VCADDQ_ROT270_M_F))
FUNCTION (vcmlaq, unspec_mve_function_exact_insn_rot, (-1, -1, UNSPEC_VCMLA, -1, -1, VCMLAQ_M_F))
FUNCTION (vcmlaq_rot90, unspec_mve_function_exact_insn_rot, (-1, -1, UNSPEC_VCMLA90, -1, -1, VCMLAQ_ROT90_M_F))
FUNCTION (vcmlaq_rot180, unspec_mve_function_exact_insn_rot, (-1, -1, UNSPEC_VCMLA180, -1, -1, VCMLAQ_ROT180_M_F))
diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def
index 43dacc3dda1..6ac1812c697 100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -523,8 +523,8 @@ VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhsubq_m_n_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhaddq_m_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhaddq_m_n_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, veorq_m_u, v16qi, v8hi, v4si)
-VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vcaddq_rot90_m_u, v16qi, v8hi, v4si)
-VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vcaddq_rot270_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vcaddq_rot90_m_, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vcaddq_rot270_m_, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vbicq_m_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vandq_m_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vaddq_m_u, v16qi, v8hi, v4si)
@@ -587,8 +587,6 @@ VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhcaddq_rot270_m_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhaddq_m_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhaddq_m_n_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, veorq_m_s, v16qi, v8hi, v4si)
-VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcaddq_rot90_m_s, v16qi, v8hi, v4si)
-VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcaddq_rot270_m_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbrsrq_m_n_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbicq_m_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vandq_m_s, v16qi, v8hi, v4si)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index b13ff53d36f..2edd0b06370 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -941,8 +941,8 @@
(VBICQ_N_S "vbic") (VBICQ_N_U "vbic")
(VBRSRQ_M_N_S "vbrsr") (VBRSRQ_M_N_U "vbrsr") (VBRSRQ_M_N_F "vbrsr")
(VBRSRQ_N_S "vbrsr") (VBRSRQ_N_U "vbrsr") (VBRSRQ_N_F "vbrsr")
- (VCADDQ_ROT270_M_U "vcadd") (VCADDQ_ROT270_M_S "vcadd") (VCADDQ_ROT270_M_F "vcadd")
- (VCADDQ_ROT90_M_U "vcadd") (VCADDQ_ROT90_M_S "vcadd") (VCADDQ_ROT90_M_F "vcadd")
+ (VCADDQ_ROT270_M "vcadd") (VCADDQ_ROT270_M_F "vcadd")
+ (VCADDQ_ROT90_M "vcadd") (VCADDQ_ROT90_M_F "vcadd")
(VCLSQ_M_S "vcls")
(VCLSQ_S "vcls")
(VCLZQ_M_S "vclz") (VCLZQ_M_U "vclz")
@@ -1215,8 +1215,8 @@
(define_int_attr isu [
(UNSPEC_VCADD90 "i") (UNSPEC_VCADD270 "i")
(VABSQ_M_S "s")
- (VCADDQ_ROT270_M_U "i") (VCADDQ_ROT270_M_S "i")
- (VCADDQ_ROT90_M_U "i") (VCADDQ_ROT90_M_S "i")
+ (VCADDQ_ROT270_M "i")
+ (VCADDQ_ROT90_M "i")
(VCLSQ_M_S "s")
(VCLZQ_M_S "i")
(VCLZQ_M_U "i")
@@ -2184,11 +2184,9 @@
(define_int_attr rot [(UNSPEC_VCADD90 "90")
(UNSPEC_VCADD270 "270")
(VCADDQ_ROT90_M_F "90")
- (VCADDQ_ROT90_M_S "90")
- (VCADDQ_ROT90_M_U "90")
+ (VCADDQ_ROT90_M "90")
(VCADDQ_ROT270_M_F "270")
- (VCADDQ_ROT270_M_S "270")
- (VCADDQ_ROT270_M_U "270")
+ (VCADDQ_ROT270_M "270")
(VHCADDQ_ROT90_S "90")
(VHCADDQ_ROT270_S "270")
(VHCADDQ_ROT90_M_S "90")
@@ -2241,11 +2239,9 @@
(define_int_attr mve_rot [(UNSPEC_VCADD90 "_rot90")
(UNSPEC_VCADD270 "_rot270")
(VCADDQ_ROT90_M_F "_rot90")
- (VCADDQ_ROT90_M_S "_rot90")
- (VCADDQ_ROT90_M_U "_rot90")
+ (VCADDQ_ROT90_M "_rot90")
(VCADDQ_ROT270_M_F "_rot270")
- (VCADDQ_ROT270_M_S "_rot270")
- (VCADDQ_ROT270_M_U "_rot270")
+ (VCADDQ_ROT270_M "_rot270")
(VHCADDQ_ROT90_S "_rot90")
(VHCADDQ_ROT270_S "_rot270")
(VHCADDQ_ROT90_M_S "_rot90")
@@ -2403,7 +2399,7 @@
(VCVTQ_M_N_TO_F_U "u") (VADDQ_M_N_U "u")
(VSHLQ_M_N_S "s") (VMAXQ_M_U "u") (VHSUBQ_M_N_U "u")
(VMULQ_M_N_S "s") (VQSHLQ_M_U "u") (VRHADDQ_M_S "s")
- (VEORQ_M_U "u") (VSHRQ_M_N_U "u") (VCADDQ_ROT90_M_U "u")
+ (VEORQ_M_U "u") (VSHRQ_M_N_U "u")
(VMLADAVAQ_P_U "u") (VEORQ_M_S "s") (VBRSRQ_M_N_S "s")
(VMULQ_M_U "u") (VQRDMLAHQ_M_N_S "s") (VHSUBQ_M_N_S "s")
(VQRSHLQ_M_S "s") (VMULQ_M_N_U "u")
@@ -2412,17 +2408,17 @@
(VMULLBQ_INT_M_U "u") (VSHLQ_M_N_U "u") (VQSUBQ_M_U "u")
(VQDMLASHQ_M_N_S "s")
(VQRDMLASHQ_M_N_U "u") (VRSHRQ_M_N_S "s")
- (VORNQ_M_S "s") (VCADDQ_ROT270_M_S "s") (VRHADDQ_M_U "u")
+ (VORNQ_M_S "s") (VCADDQ_ROT270_M "") (VRHADDQ_M_U "u")
(VRSHRQ_M_N_U "u") (VMLASQ_M_N_U "u") (VHSUBQ_M_U "u")
(VQSUBQ_M_N_S "s") (VMULLTQ_INT_M_S "s")
(VORRQ_M_S "s") (VQDMLAHQ_M_N_U "u") (VRSHLQ_M_S "s")
(VHADDQ_M_U "u") (VHADDQ_M_N_S "s") (VMULLTQ_INT_M_U "u")
(VORRQ_M_U "u") (VHADDQ_M_S "s") (VHADDQ_M_N_U "u")
(VQDMLAHQ_M_N_S "s") (VMAXQ_M_S "s") (VORNQ_M_U "u")
- (VCADDQ_ROT270_M_U "u") (VQADDQ_M_U "u")
+ (VQADDQ_M_U "u")
(VQRDMLASHQ_M_N_S "s") (VBICQ_M_U "u") (VMINQ_M_U "u")
(VSUBQ_M_N_S "s") (VMULLBQ_INT_M_S "s") (VQSUBQ_M_S "s")
- (VCADDQ_ROT90_M_S "s") (VRMULHQ_M_S "s") (VANDQ_M_U "u")
+ (VCADDQ_ROT90_M "") (VRMULHQ_M_S "s") (VANDQ_M_U "u")
(VMULHQ_M_S "s") (VADDQ_M_S "s") (VQRDMLAHQ_M_N_U "u")
(VMLASQ_M_N_S "s") (VHSUBQ_M_S "s") (VRMULHQ_M_U "u")
(VQADDQ_M_N_S "s") (VSHRQ_M_N_S "s") (VANDQ_M_S "s")
@@ -2834,7 +2830,7 @@
(define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U])
(define_int_iterator VCADDQ_M_F [VCADDQ_ROT90_M_F VCADDQ_ROT270_M_F])
(define_int_iterator VxCADDQ [UNSPEC_VCADD90 UNSPEC_VCADD270 VHCADDQ_ROT90_S VHCADDQ_ROT270_S])
-(define_int_iterator VxCADDQ_M [VHCADDQ_ROT90_M_S VHCADDQ_ROT270_M_S VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
+(define_int_iterator VxCADDQ_M [VHCADDQ_ROT90_M_S VHCADDQ_ROT270_M_S VCADDQ_ROT90_M VCADDQ_ROT270_M])
(define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S])
(define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S])
(define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index a2cbcff1a6f..6e4b143affa 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -839,8 +839,8 @@
])
;;
-;; [vcaddq_rot90_s, vcadd_rot90_u]
-;; [vcaddq_rot270_s, vcadd_rot270_u]
+;; [vcaddq_rot90_s, vcaddq_rot90_u]
+;; [vcaddq_rot270_s, vcaddq_rot270_u]
;; [vhcaddq_rot90_s]
;; [vhcaddq_rot270_s]
;;
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index dccda283573..6a5b1f8f623 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -995,8 +995,7 @@
VMAXQ_M_U
VQRDMLAHQ_M_N_U
VCADDQ_ROT270_M_F
- VCADDQ_ROT270_M_U
- VCADDQ_ROT270_M_S
+ VCADDQ_ROT270_M
VQRSHLQ_M_S
VMULQ_M_F
VRHADDQ_M_U
@@ -1050,8 +1049,7 @@
VSLIQ_M_N_S
VQSHLQ_M_U
VQSHLQ_M_S
- VCADDQ_ROT90_M_U
- VCADDQ_ROT90_M_S
+ VCADDQ_ROT90_M
VORNQ_M_U
VORNQ_M_S
VQSHLQ_M_N_S
--
2.34.1
