LGTM, that's a really great clean up :)
On Sat, Nov 18, 2023 at 11:12 AM Juzhe-Zhong <juzhe.zh...@rivai.ai> wrote: > > This patch refactors RVV iteratros for easier maintain. > > E.g. > > (define_mode_iterator V [ > RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI > "TARGET_MIN_VLEN > 32") > > RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") > > (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") > (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") > (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") > (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > > RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") > > (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") > (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") > (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && > TARGET_MIN_VLEN > 32") > > (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") > (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > > (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") > (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") > ]) > > change it into: > > (define_mode_iterator V [VI VF_ZVFHMIN]) > > gcc/ChangeLog: > > * config/riscv/vector-iterators.md: Refactor iterators. > > --- > gcc/config/riscv/vector-iterators.md | 661 +++++---------------------- > 1 file changed, 124 insertions(+), 537 deletions(-) > > diff --git a/gcc/config/riscv/vector-iterators.md > b/gcc/config/riscv/vector-iterators.md > index f04c7fe5491..469875ce67c 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -108,48 +108,49 @@ > UNSPECV_FRM_RESTORE_EXIT > ]) > > -(define_mode_iterator V [ > +(define_mode_iterator VI [ > RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI > "TARGET_MIN_VLEN > 32") > > RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") > > - (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") > (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > - > RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") > > - (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") > (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 > && TARGET_MIN_VLEN > 32") > - > (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") > (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > +]) > + > +;; This iterator is the same as above but with TARGET_VECTOR_ELEN_FP_16 > +;; changed to TARGET_ZVFH. TARGET_VECTOR_ELEN_FP_16 is also true for > +;; TARGET_ZVFHMIN while we actually want to disable all instructions apart > +;; from load, store and convert for it. > +;; It is not enough to set the "enabled" attribute to false > +;; since this will only disable insn alternatives in reload but still > +;; allow the instruction and mode to be matched during combine et al. > +(define_mode_iterator VF [ > + (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") > + (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") > + (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") > + > + (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") > (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") > + (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 > && TARGET_MIN_VLEN > 32") > > (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") > (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") > ]) > > -(define_mode_iterator V_VLS [ > - RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI > "TARGET_MIN_VLEN > 32") > - > - RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") > - > +(define_mode_iterator VF_ZVFHMIN [ > (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") > (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") > (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") > (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > > - RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") > - > (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") > (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") > (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 > && TARGET_MIN_VLEN > 32") > > - (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") > - (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > - > (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") > (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") > +]) > > - ;; VLS modes. > +(define_mode_iterator VLSI [ > (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)") > (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)") > (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)") > @@ -195,7 +196,45 @@ > (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512") > (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024") > (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048") > - (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096") > + (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")]) > + > +(define_mode_iterator VLSF [ > + (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH") > + (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH") > + (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH") > + (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH") > + (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH") > + (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 64") > + (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 128") > + (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 256") > + (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 512") > + (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 1024") > + (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 2048") > + (V2048HF "riscv_vector::vls_mode_valid_p (V2048HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 4096") > + (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && > TARGET_VECTOR_ELEN_FP_32") > + (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && > TARGET_VECTOR_ELEN_FP_32") > + (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && > TARGET_VECTOR_ELEN_FP_32") > + (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && > TARGET_VECTOR_ELEN_FP_32") > + (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") > + (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > + (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") > + (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") > + (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") > + (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") > + (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") > + (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && > TARGET_VECTOR_ELEN_FP_64") > + (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && > TARGET_VECTOR_ELEN_FP_64") > + (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && > TARGET_VECTOR_ELEN_FP_64") > + (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64") > + (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") > + (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256") > + (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512") > + (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024") > + (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") > + (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096") > +]) > + > +(define_mode_iterator VLSF_ZVFHMIN [ > (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && > TARGET_VECTOR_ELEN_FP_16") > (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && > TARGET_VECTOR_ELEN_FP_16") > (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && > TARGET_VECTOR_ELEN_FP_16") > @@ -399,196 +438,6 @@ > (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096") > ]) > > -(define_mode_iterator VI [ > - RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI > "TARGET_MIN_VLEN > 32") > - > - RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") > - > - RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") > - > - (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") > - (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > -]) > - > -(define_mode_iterator V_VLSI [ > - RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI > "TARGET_MIN_VLEN > 32") > - > - RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") > - > - RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") > - > - (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") > - (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > - > - (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)") > - (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)") > - (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)") > - (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)") > - (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)") > - (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)") > - (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= > 64") > - (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= > 128") > - (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= > 256") > - (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= > 512") > - (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN > >= 1024") > - (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN > >= 2048") > - (V4096QI "riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN > >= 4096") > - (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)") > - (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)") > - (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)") > - (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)") > - (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)") > - (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= > 64") > - (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= > 128") > - (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= > 256") > - (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= > 512") > - (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= > 1024") > - (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN > >= 2048") > - (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN > >= 4096") > - (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)") > - (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)") > - (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)") > - (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)") > - (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= > 64") > - (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= > 128") > - (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= > 256") > - (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= > 512") > - (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= > 1024") > - (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= > 2048") > - (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN > >= 4096") > - (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64") > - (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64") > - (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64") > - (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 > && TARGET_MIN_VLEN >= 64") > - (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > - (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256") > - (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512") > - (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024") > - (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048") > - (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096") > -]) > - > -(define_mode_iterator V_VLSF [ > - (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") > - (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") > - (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") > - (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") > (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 > && TARGET_MIN_VLEN > 32") > - (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") > - > - (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH") > - (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH") > - (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH") > - (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH") > - (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH") > - (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 64") > - (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 128") > - (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 256") > - (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 512") > - (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 1024") > - (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 2048") > - (V2048HF "riscv_vector::vls_mode_valid_p (V2048HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 4096") > - (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") > - (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > - (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") > - (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") > - (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") > - (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") > - (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") > - (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64") > - (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") > - (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256") > - (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512") > - (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024") > - (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") > - (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096") > -]) > - > -(define_mode_iterator VF_ZVFHMIN [ > - (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") > (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > - > - (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") > (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 > && TARGET_MIN_VLEN > 32") > - > - (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") > -]) > - > -(define_mode_iterator V_VLSF_ZVFHMIN [ > - (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") > (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > - > - (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") > (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 > && TARGET_MIN_VLEN > 32") > - > - (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") > - > - (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && > TARGET_VECTOR_ELEN_FP_16") > - (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && > TARGET_VECTOR_ELEN_FP_16") > - (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && > TARGET_VECTOR_ELEN_FP_16") > - (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && > TARGET_VECTOR_ELEN_FP_16") > - (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && > TARGET_VECTOR_ELEN_FP_16") > - (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") > - (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") > - (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256") > - (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512") > - (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024") > - (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048") > - (V2048HF "riscv_vector::vls_mode_valid_p (V2048HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096") > - (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") > - (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > - (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") > - (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") > - (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") > - (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") > - (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") > - (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64") > - (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") > - (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256") > - (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512") > - (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024") > - (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") > - (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096") > -]) > - > -;; This iterator is the same as above but with TARGET_VECTOR_ELEN_FP_16 > -;; changed to TARGET_ZVFH. TARGET_VECTOR_ELEN_FP_16 is also true for > -;; TARGET_ZVFHMIN while we actually want to disable all instructions apart > -;; from load, store and convert for it. > -;; It is not enough to set the "enabled" attribute to false > -;; since this will only disable insn alternatives in reload but still > -;; allow the instruction and mode to be matched during combine et al. > -(define_mode_iterator VF [ > - (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") > - (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") > - (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") > - > - (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") > (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 > && TARGET_MIN_VLEN > 32") > - > - (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") > -]) > - > (define_mode_iterator VFULLI [ > RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI > "TARGET_MIN_VLEN > 32") > > @@ -1011,27 +860,6 @@ > (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") > ]) > > -(define_mode_iterator VB [ > - (RVVMF64BI "TARGET_MIN_VLEN > 32") RVVMF32BI RVVMF16BI RVVMF8BI RVVMF4BI > RVVMF2BI RVVM1BI > -]) > - > -(define_mode_iterator VB_VLS [ > - (RVVMF64BI "TARGET_MIN_VLEN > 32") RVVMF32BI RVVMF16BI RVVMF8BI RVVMF4BI > RVVMF2BI RVVM1BI > - (V1BI "riscv_vector::vls_mode_valid_p (V1BImode)") > - (V2BI "riscv_vector::vls_mode_valid_p (V2BImode)") > - (V4BI "riscv_vector::vls_mode_valid_p (V4BImode)") > - (V8BI "riscv_vector::vls_mode_valid_p (V8BImode)") > - (V16BI "riscv_vector::vls_mode_valid_p (V16BImode)") > - (V32BI "riscv_vector::vls_mode_valid_p (V32BImode)") > - (V64BI "riscv_vector::vls_mode_valid_p (V64BImode) && TARGET_MIN_VLEN >= > 64") > - (V128BI "riscv_vector::vls_mode_valid_p (V128BImode) && TARGET_MIN_VLEN >= > 128") > - (V256BI "riscv_vector::vls_mode_valid_p (V256BImode) && TARGET_MIN_VLEN >= > 256") > - (V512BI "riscv_vector::vls_mode_valid_p (V512BImode) && TARGET_MIN_VLEN >= > 512") > - (V1024BI "riscv_vector::vls_mode_valid_p (V1024BImode) && TARGET_MIN_VLEN > >= 1024") > - (V2048BI "riscv_vector::vls_mode_valid_p (V2048BImode) && TARGET_MIN_VLEN > >= 2048") > - (V4096BI "riscv_vector::vls_mode_valid_p (V4096BImode) && TARGET_MIN_VLEN > >= 4096") > -]) > - > (define_mode_iterator VWEXTI [ > RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") > > @@ -1219,133 +1047,38 @@ > (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024") > (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048") > (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096") > -]) > - > -(define_mode_iterator VQEXTF [ > - (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") > - > - (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64") > - (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") > - (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256") > - (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512") > - (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024") > - (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") > - (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096") > -]) > - > -(define_mode_iterator VOEXTI [ > - (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") > - (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > - > - (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64") > - (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64") > - (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64") > - (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 > && TARGET_MIN_VLEN >= 64") > - (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > - (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256") > - (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512") > - (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024") > - (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048") > - (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096") > -]) > - > -(define_mode_iterator VT [ > - RVVM1x8QI RVVMF2x8QI RVVMF4x8QI (RVVMF8x8QI "TARGET_MIN_VLEN > 32") > - RVVM1x7QI RVVMF2x7QI RVVMF4x7QI (RVVMF8x7QI "TARGET_MIN_VLEN > 32") > - RVVM1x6QI RVVMF2x6QI RVVMF4x6QI (RVVMF8x6QI "TARGET_MIN_VLEN > 32") > - RVVM1x5QI RVVMF2x5QI RVVMF4x5QI (RVVMF8x5QI "TARGET_MIN_VLEN > 32") > - RVVM2x4QI RVVM1x4QI RVVMF2x4QI RVVMF4x4QI (RVVMF8x4QI "TARGET_MIN_VLEN > > 32") > - RVVM2x3QI RVVM1x3QI RVVMF2x3QI RVVMF4x3QI (RVVMF8x3QI "TARGET_MIN_VLEN > > 32") > - RVVM4x2QI RVVM2x2QI RVVM1x2QI RVVMF2x2QI RVVMF4x2QI (RVVMF8x2QI > "TARGET_MIN_VLEN > 32") > - > - RVVM1x8HI RVVMF2x8HI (RVVMF4x8HI "TARGET_MIN_VLEN > 32") > - RVVM1x7HI RVVMF2x7HI (RVVMF4x7HI "TARGET_MIN_VLEN > 32") > - RVVM1x6HI RVVMF2x6HI (RVVMF4x6HI "TARGET_MIN_VLEN > 32") > - RVVM1x5HI RVVMF2x5HI (RVVMF4x5HI "TARGET_MIN_VLEN > 32") > - RVVM2x4HI RVVM1x4HI RVVMF2x4HI (RVVMF4x4HI "TARGET_MIN_VLEN > 32") > - RVVM2x3HI RVVM1x3HI RVVMF2x3HI (RVVMF4x3HI "TARGET_MIN_VLEN > 32") > - RVVM4x2HI RVVM2x2HI RVVM1x2HI RVVMF2x2HI (RVVMF4x2HI "TARGET_MIN_VLEN > > 32") > - > - (RVVM1x8HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF2x8HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF4x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > - (RVVM1x7HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF2x7HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF4x7HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > - (RVVM1x6HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF2x6HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF4x6HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > - (RVVM1x5HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF2x5HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF4x5HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > - (RVVM2x4HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVM1x4HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF2x4HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF4x4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > - (RVVM2x3HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVM1x3HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF2x3HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF4x3HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > - (RVVM4x2HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVM2x2HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVM1x2HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF2x2HF "TARGET_VECTOR_ELEN_FP_16") > - (RVVMF4x2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > - > - RVVM1x8SI (RVVMF2x8SI "TARGET_MIN_VLEN > 32") > - RVVM1x7SI (RVVMF2x7SI "TARGET_MIN_VLEN > 32") > - RVVM1x6SI (RVVMF2x6SI "TARGET_MIN_VLEN > 32") > - RVVM1x5SI (RVVMF2x5SI "TARGET_MIN_VLEN > 32") > - RVVM2x4SI RVVM1x4SI (RVVMF2x4SI "TARGET_MIN_VLEN > 32") > - RVVM2x3SI RVVM1x3SI (RVVMF2x3SI "TARGET_MIN_VLEN > 32") > - RVVM4x2SI RVVM2x2SI RVVM1x2SI (RVVMF2x2SI "TARGET_MIN_VLEN > 32") > - > - (RVVM1x8SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVMF2x8SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") > - (RVVM1x7SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVMF2x7SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") > - (RVVM1x6SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVMF2x6SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") > - (RVVM1x5SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVMF2x5SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") > - (RVVM2x4SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVM1x4SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVMF2x4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") > - (RVVM2x3SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVM1x3SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVMF2x3SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") > - (RVVM4x2SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVM2x2SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVM1x2SF "TARGET_VECTOR_ELEN_FP_32") > - (RVVMF2x2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") > +]) > > - (RVVM1x8DI "TARGET_VECTOR_ELEN_64") > - (RVVM1x7DI "TARGET_VECTOR_ELEN_64") > - (RVVM1x6DI "TARGET_VECTOR_ELEN_64") > - (RVVM1x5DI "TARGET_VECTOR_ELEN_64") > - (RVVM2x4DI "TARGET_VECTOR_ELEN_64") > - (RVVM1x4DI "TARGET_VECTOR_ELEN_64") > - (RVVM2x3DI "TARGET_VECTOR_ELEN_64") > - (RVVM1x3DI "TARGET_VECTOR_ELEN_64") > - (RVVM4x2DI "TARGET_VECTOR_ELEN_64") > - (RVVM2x2DI "TARGET_VECTOR_ELEN_64") > - (RVVM1x2DI "TARGET_VECTOR_ELEN_64") > +(define_mode_iterator VQEXTF [ > + (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") > + (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") > > - (RVVM1x8DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM1x7DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM1x6DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM1x5DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM2x4DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM1x4DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM2x3DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM1x3DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM4x2DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM2x2DF "TARGET_VECTOR_ELEN_FP_64") > - (RVVM1x2DF "TARGET_VECTOR_ELEN_FP_64") > + (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && > TARGET_VECTOR_ELEN_FP_64") > + (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && > TARGET_VECTOR_ELEN_FP_64") > + (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && > TARGET_VECTOR_ELEN_FP_64") > + (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64") > + (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") > + (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256") > + (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512") > + (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024") > + (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") > + (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096") > +]) > + > +(define_mode_iterator VOEXTI [ > + (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") > + (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > + > + (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64") > + (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64") > + (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64") > + (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 > && TARGET_MIN_VLEN >= 64") > + (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > + (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256") > + (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512") > + (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024") > + (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048") > + (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096") > ]) > > (define_mode_iterator V1T [ > @@ -1674,6 +1407,41 @@ > (V1024SF "RVVM1DF") > ]) > > +(define_mode_iterator VLSB [ > + (V1BI "riscv_vector::vls_mode_valid_p (V1BImode)") > + (V2BI "riscv_vector::vls_mode_valid_p (V2BImode)") > + (V4BI "riscv_vector::vls_mode_valid_p (V4BImode)") > + (V8BI "riscv_vector::vls_mode_valid_p (V8BImode)") > + (V16BI "riscv_vector::vls_mode_valid_p (V16BImode)") > + (V32BI "riscv_vector::vls_mode_valid_p (V32BImode)") > + (V64BI "riscv_vector::vls_mode_valid_p (V64BImode) && TARGET_MIN_VLEN >= > 64") > + (V128BI "riscv_vector::vls_mode_valid_p (V128BImode) && TARGET_MIN_VLEN >= > 128") > + (V256BI "riscv_vector::vls_mode_valid_p (V256BImode) && TARGET_MIN_VLEN >= > 256") > + (V512BI "riscv_vector::vls_mode_valid_p (V512BImode) && TARGET_MIN_VLEN >= > 512") > + (V1024BI "riscv_vector::vls_mode_valid_p (V1024BImode) && TARGET_MIN_VLEN > >= 1024") > + (V2048BI "riscv_vector::vls_mode_valid_p (V2048BImode) && TARGET_MIN_VLEN > >= 2048") > + (V4096BI "riscv_vector::vls_mode_valid_p (V4096BImode) && TARGET_MIN_VLEN > >= 4096")]) > + > +(define_mode_iterator VB [ > + (RVVMF64BI "TARGET_MIN_VLEN > 32") RVVMF32BI RVVMF16BI RVVMF8BI RVVMF4BI > RVVMF2BI RVVM1BI > +]) > + > +(define_mode_iterator VB_VLS [VB VLSB]) > + > +(define_mode_iterator VLS [VLSI VLSF_ZVFHMIN]) > + > +(define_mode_iterator V [VI VF_ZVFHMIN]) > + > +(define_mode_iterator V_VLS [V VLS]) > + > +(define_mode_iterator V_VLSI [VI VLSI]) > + > +(define_mode_iterator V_VLSF [VF VLSF]) > + > +(define_mode_iterator V_VLSF_ZVFHMIN [VF_ZVFHMIN VLSF_ZVFHMIN]) > + > +(define_mode_iterator VT [V1T V2T V4T V8T V16T V32T]) > + > (define_int_iterator ANY_REDUC [ > UNSPEC_REDUC_SUM UNSPEC_REDUC_MAXU UNSPEC_REDUC_MAX UNSPEC_REDUC_MINU > UNSPEC_REDUC_MIN UNSPEC_REDUC_AND UNSPEC_REDUC_OR UNSPEC_REDUC_XOR > @@ -3941,103 +3709,6 @@ > > (define_code_attr sz [(sign_extend "s") (zero_extend "z")]) > > -;; VLS modes. > -(define_mode_iterator VLS [ > - (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)") > - (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)") > - (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)") > - (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)") > - (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)") > - (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)") > - (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= > 64") > - (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= > 128") > - (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= > 256") > - (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= > 512") > - (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN > >= 1024") > - (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN > >= 2048") > - (V4096QI "riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN > >= 4096") > - (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)") > - (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)") > - (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)") > - (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)") > - (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)") > - (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= > 64") > - (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= > 128") > - (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= > 256") > - (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= > 512") > - (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= > 1024") > - (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN > >= 2048") > - (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN > >= 4096") > - (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)") > - (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)") > - (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)") > - (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)") > - (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= > 64") > - (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= > 128") > - (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= > 256") > - (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= > 512") > - (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= > 1024") > - (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= > 2048") > - (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN > >= 4096") > - (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64") > - (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64") > - (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64") > - (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 > && TARGET_MIN_VLEN >= 64") > - (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > - (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256") > - (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512") > - (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024") > - (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048") > - (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096") > - (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && > TARGET_VECTOR_ELEN_FP_16") > - (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && > TARGET_VECTOR_ELEN_FP_16") > - (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && > TARGET_VECTOR_ELEN_FP_16") > - (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && > TARGET_VECTOR_ELEN_FP_16") > - (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && > TARGET_VECTOR_ELEN_FP_16") > - (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") > - (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") > - (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256") > - (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512") > - (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024") > - (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048") > - (V2048HF "riscv_vector::vls_mode_valid_p (V2048HFmode) && > TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096") > - (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") > - (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > - (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") > - (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") > - (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") > - (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") > - (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") > - (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64") > - (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") > - (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256") > - (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512") > - (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024") > - (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") > - (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")]) > - > -(define_mode_iterator VLSB [ > - (V1BI "riscv_vector::vls_mode_valid_p (V1BImode)") > - (V2BI "riscv_vector::vls_mode_valid_p (V2BImode)") > - (V4BI "riscv_vector::vls_mode_valid_p (V4BImode)") > - (V8BI "riscv_vector::vls_mode_valid_p (V8BImode)") > - (V16BI "riscv_vector::vls_mode_valid_p (V16BImode)") > - (V32BI "riscv_vector::vls_mode_valid_p (V32BImode)") > - (V64BI "riscv_vector::vls_mode_valid_p (V64BImode) && TARGET_MIN_VLEN >= > 64") > - (V128BI "riscv_vector::vls_mode_valid_p (V128BImode) && TARGET_MIN_VLEN >= > 128") > - (V256BI "riscv_vector::vls_mode_valid_p (V256BImode) && TARGET_MIN_VLEN >= > 256") > - (V512BI "riscv_vector::vls_mode_valid_p (V512BImode) && TARGET_MIN_VLEN >= > 512") > - (V1024BI "riscv_vector::vls_mode_valid_p (V1024BImode) && TARGET_MIN_VLEN > >= 1024") > - (V2048BI "riscv_vector::vls_mode_valid_p (V2048BImode) && TARGET_MIN_VLEN > >= 2048") > - (V4096BI "riscv_vector::vls_mode_valid_p (V4096BImode) && TARGET_MIN_VLEN > >= 4096")]) > - > ;; VLS modes that has NUNITS < 32. > (define_mode_iterator VLS_AVL_IMM [ > (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)") > @@ -4137,87 +3808,3 @@ > (V1024BI "riscv_vector::vls_mode_valid_p (V1024BImode) && TARGET_MIN_VLEN > >= 1024") > (V2048BI "riscv_vector::vls_mode_valid_p (V2048BImode) && TARGET_MIN_VLEN > >= 2048") > (V4096BI "riscv_vector::vls_mode_valid_p (V4096BImode) && TARGET_MIN_VLEN > >= 4096")]) > - > -(define_mode_iterator VLSI [ > - (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)") > - (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)") > - (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)") > - (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)") > - (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)") > - (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)") > - (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= > 64") > - (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= > 128") > - (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= > 256") > - (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= > 512") > - (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN > >= 1024") > - (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN > >= 2048") > - (V4096QI "riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN > >= 4096") > - (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)") > - (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)") > - (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)") > - (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)") > - (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)") > - (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= > 64") > - (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= > 128") > - (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= > 256") > - (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= > 512") > - (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= > 1024") > - (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN > >= 2048") > - (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN > >= 4096") > - (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)") > - (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)") > - (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)") > - (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)") > - (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= > 64") > - (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= > 128") > - (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= > 256") > - (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= > 512") > - (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= > 1024") > - (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= > 2048") > - (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN > >= 4096") > - (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64") > - (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64") > - (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64") > - (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 > && TARGET_MIN_VLEN >= 64") > - (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > - (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256") > - (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512") > - (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024") > - (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048") > - (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && > TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")]) > - > -(define_mode_iterator VLSF [ > - (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH") > - (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH") > - (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH") > - (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH") > - (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH") > - (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 64") > - (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 128") > - (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 256") > - (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 512") > - (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 1024") > - (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 2048") > - (V2048HF "riscv_vector::vls_mode_valid_p (V2048HFmode) && TARGET_ZVFH && > TARGET_MIN_VLEN >= 4096") > - (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && > TARGET_VECTOR_ELEN_FP_32") > - (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") > - (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > - (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") > - (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") > - (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") > - (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") > - (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") > - (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && > TARGET_VECTOR_ELEN_FP_64") > - (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64") > - (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") > - (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256") > - (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512") > - (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024") > - (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") > - (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && > TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096") > -]) > -- > 2.36.3 >