On Fri, 8 Dec 2023, Haochen Jiang wrote: > +++ b/htdocs/gcc-13/changes.html
> + Based on ISA extensions enabled on Alder Lake, the switch further enables > + the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, ENQCMD and UINTR > + ISA extensions. Personally I would alphabetically sort all the options, like you have mostly done already. Just AVX-VNNI-INT8 and AVX-NE-CONVERT are not. (Maybe you have a reason, and in any case this should not block this patch.) > +++ b/htdocs/gcc-14/changes.html > + <li>New ISA extension support for Intel AVX10.1 was added. > + AVX10.1 intrinsics are available via the <code>-mavx10.1</code> or > + <code>-mavx10.1-256</code> compiler switch with 256 bit vector size > + support. 512 bit vector size support for AVX10.1 intrinsics are We usually write 256-bit and 512-bit as adjectives, cf. gcc.gnu.org/codingconventions.html . > + <li>Part of new feature support for Intel APX was added, including EGPR, > + PUSH2POP2, PPX and NDD. Alphabetically? > APX features are available via the > + <code>-mapxf</code> compiler switch. Could we say "APX is enabled via..." or "APX support is available via..."? > + <li>Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are > marked > + as deprecated. GCC will emit a warning when using the > + <code>-mavx5124fmaps</code>, <code>-mavx5124vnniw</code>, > + <code>-mavx512er</code>, <code>-mavx512pf</code>, > + <code>-mprefetchwt1</code>, <code>-march=knl</code>, > + <code>-march=knm</code>, <code>-mtune=knl</code> and > <code>-mtune=knm</code> > + compiler switch. The support will be removed in GCC 15. > + </li> I believe "or" instead of "and" will be clearer. And "compiler switches" (plural). And just "Support" in the last sentence. Thanks for submitting these! No need for further review before committing (a minor variation). Gerald
