LGTM now, thanks. I find it much more readable that way.
Regards Robin
- [PATCH v4] RISC-V: Fix register overlap issue fo... Jun Sha (Joshua)
- [PATCH v5] RISC-V: Fix register overlap issu... Jun Sha (Joshua)
- Re: [PATCH v5] RISC-V: Fix register over... juzhe.zh...@rivai.ai
- [PATCH v5] RISC-V: Fix register overlap issu... Jun Sha (Joshua)
- Re: [PATCH v5] RISC-V: Fix register over... juzhe.zh...@rivai.ai
- Re: [PATCH v5] RISC-V: Fix register over... Robin Dapp
- [PATCH v5] RISC-V: Fix register overlap ... Jun Sha (Joshua)
- Re: [PATCH v5] RISC-V: Fix register ... juzhe.zh...@rivai.ai
- Re: [PATCH v5] RISC-V: Fix regi... Robin Dapp
- [PATCH v4] RISC-V: Rewrite some instructions using AS... Jun Sha (Joshua)
- Re: [PATCH v4] RISC-V: Rewrite some instructions... Kito Cheng
- [PATCH v4] RISC-V: Rewrite some instructions usi... Jun Sha (Joshua)
- [PATCH v5] RISC-V: Support XTheadVector extension Jun Sha (Joshua)
- [PATCH v4] RISC-V: Introduce XTheadVector as a s... Jun Sha (Joshua)
- Re: [PATCH v4] RISC-V: Introduce XTheadVecto... juzhe.zh...@rivai.ai
- Re: [PATCH v4] RISC-V: Introduce XTheadV... Kito Cheng
- [PATCH v5] RISC-V: Adds the prefix "th.&quo... Jun Sha (Joshua)
- Re: [PATCH v5] RISC-V: Adds the prefix "... juzhe.zh...@rivai.ai
- [PATCH v6] RISC-V: Handle differences between XT... Jun Sha (Joshua)
