[PATCH] arm: [MVE intrinsics] Fix support for predicate constants [PR target/114801]

[Christophe Lyon]

In this PR, we have to handle a case where MVE predicates are supplied
as a const_int, where individual predicates have illegal boolean
values (such as 0xc for a 4-bit boolean predicate).  To avoid the ICE,
we canonicalize them, replacing a non-null value with -1.

2024-04-26  Christophe Lyon  <christophe.l...@linaro.org>
            Jakub Jelinek  <ja...@redhat.com>

        PR target/114801
        gcc/
        * config/arm/arm-mve-builtins.cc
        (function_expander::add_input_operand): Handle CONST_INT
        predicates.

        gcc/testsuite/
        * gcc.target/arm/mve/pr114801.c: New test.
---
 gcc/config/arm/arm-mve-builtins.cc          | 21 +++++++++++-
 gcc/testsuite/gcc.target/arm/mve/pr114801.c | 36 +++++++++++++++++++++
 2 files changed, 56 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr114801.c

diff --git a/gcc/config/arm/arm-mve-builtins.cc 
b/gcc/config/arm/arm-mve-builtins.cc
index 6a5775c67e5..f338ab36434 100644
--- a/gcc/config/arm/arm-mve-builtins.cc
+++ b/gcc/config/arm/arm-mve-builtins.cc
@@ -43,6 +43,7 @@
 #include "stringpool.h"
 #include "attribs.h"
 #include "diagnostic.h"
+#include "rtx-vector-builder.h"
 #include "arm-protos.h"
 #include "arm-builtins.h"
 #include "arm-mve-builtins.h"
@@ -2205,7 +2206,25 @@ function_expander::add_input_operand (insn_code icode, 
rtx x)
       mode = GET_MODE (x);
     }
   else if (VALID_MVE_PRED_MODE (mode))
-    x = gen_lowpart (mode, x);
+    {
+      if (CONST_INT_P (x) && (mode == V8BImode || mode == V4BImode))
+       {
+         /* In V8BI or V4BI each element has 2 or 4 bits, if those
+            bits aren't all the same, it is UB and gen_lowpart might
+            ICE.  Canonicalize all the 2 or 4 bits to all ones if any
+            of them is non-zero.  */
+         unsigned HOST_WIDE_INT xi = UINTVAL (x);
+         xi |= ((xi & 0x5555) << 1) | ((xi & 0xaaaa) >> 1);
+         if (mode == V4BImode)
+           xi |= ((xi & 0x3333) << 2) | ((xi & 0xcccc) >> 2);
+         x = gen_int_mode (xi, HImode);
+       }
+      else if (SUBREG_P (x))
+       /* gen_lowpart on a SUBREG can ICE.  */
+       x = force_reg (GET_MODE (x), x);
+
+      x = gen_lowpart (mode, x);
+    }
 
   m_ops.safe_grow (m_ops.length () + 1, true);
   create_input_operand (&m_ops.last (), x, mode);
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr114801.c 
b/gcc/testsuite/gcc.target/arm/mve/pr114801.c
new file mode 100644
index 00000000000..676b109f9b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr114801.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+#include <arm_mve.h>
+
+/*
+** test_32:
+**...
+**     mov     r[0-9]+, #65535 @ movhi
+**...
+*/
+uint32x4_t test_32() {
+  return vdupq_m_n_u32(vdupq_n_u32(0), 0, 0xcccc);
+}
+
+/*
+** test_16:
+**...
+**     mov     r[0-9]+, #52428 @ movhi
+**...
+*/
+uint16x8_t test_16() {
+  return vdupq_m_n_u16(vdupq_n_u16(0), 0, 0xcccc);
+}
+
+/*
+** test_8:
+**...
+**     mov     r[0-9]+, #52428 @ movhi
+**...
+*/
+uint8x16_t test_8() {
+  return vdupq_m_n_u8(vdupq_n_u8(0), 0, 0xcccc);
+}
-- 
2.34.1