On 5/8/24 1:36 AM, Christoph Müllner wrote:
The pattern lshrsi3_zero_extend_2 extracts the MSB bits of the lower
32-bit word and zero-extends it back to DImode.
This is realized using srliw, which operates on 32-bit registers.
The same optimziation can be applied to sign-extensions when emitting
a sraiw instead of the srliw.
Given these two optimizations are so similar, this patch simply
converts the existing one to also cover the sign-extension case as well.
gcc/ChangeLog:
* config/riscv/iterators.md (sraiw): New code iterator 'any_extract'.
New code attribute 'extract_sidi_shift'.
* config/riscv/riscv.md (*lshrsi3_zero_extend_2): Rename to...
(*lshrsi3_extend_2):...this and add support for sign-extensions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sign-extend-1.c: Test sraiw 24 and sraiw 16.
OK
jeff
