Hi,
on 2024/4/20 05:17, Carl Love wrote:
> rs6000, remove duplicated built-ins of vecmergl and vec_mergeh
>
> The following undocumented built-ins are same as existing documented
> overloaded builtins.
>
> const vf __builtin_vsx_xxmrghw (vf, vf);
> same as vf __builtin_vec_mergeh (vf, vf); (overloaded vec_mergeh)
>
> const vsi __builtin_vsx_xxmrghw_4si (vsi, vsi);
> same as vsi __builtin_vec_mergeh (vsi, vsi); (overloaded vec_mergeh)
>
> const vf __builtin_vsx_xxmrglw (vf, vf);
> same as vf __builtin_vec_mergel (vf, vf); (overloaded vec_mergel)
>
> const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi);
> same as vsi __builtin_vec_mergel (vsi, vsi); (overloaded vec_mergel)
>
> This patch removes the duplicate built-in definitions so only the
> documented built-ins will be available for use. The case statements in
> rs6000_gimple_fold_builtin are removed as they are no longer needed. The
> patch removes the now unused define_expands for vsx_xxmrghw_<mode> and
> vsx_xxmrglw_<mode>.
Ok for trunk, thanks!
BR,
Kewen
>
> gcc/ChangeLog:
> * config/rs6000/rs6000-builtins.def (__builtin_vsx_xxmrghw,
> __builtin_vsx_xxmrghw_4si, __builtin_vsx_xxmrglw,
> __builtin_vsx_xxmrglw_4si, __builtin_vsx_xxsel_16qi): Remove
> built-in definition.
> * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin):
> remove case entries RS6000_BIF_XXMRGLW_4SI,
> RS6000_BIF_XXMRGLW_4SF, RS6000_BIF_XXMRGHW_4SI,
> RS6000_BIF_XXMRGHW_4SF.
> * config/rs6000/vsx.md (vsx_xxmrghw_<mode>, vsx_xxmrglw_<mode>):
> Remove unused define_expands.
> ---
> gcc/config/rs6000/rs6000-builtin.cc | 4 ---
> gcc/config/rs6000/rs6000-builtins.def | 12 --------
> gcc/config/rs6000/vsx.md | 41 ---------------------------
> 3 files changed, 57 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
> b/gcc/config/rs6000/rs6000-builtin.cc
> index ac9f16fe51a..f83d65b06ef 100644
> --- a/gcc/config/rs6000/rs6000-builtin.cc
> +++ b/gcc/config/rs6000/rs6000-builtin.cc
> @@ -2097,20 +2097,16 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
> /* vec_mergel (integrals). */
> case RS6000_BIF_VMRGLH:
> case RS6000_BIF_VMRGLW:
> - case RS6000_BIF_XXMRGLW_4SI:
> case RS6000_BIF_VMRGLB:
> case RS6000_BIF_VEC_MERGEL_V2DI:
> - case RS6000_BIF_XXMRGLW_4SF:
> case RS6000_BIF_VEC_MERGEL_V2DF:
> fold_mergehl_helper (gsi, stmt, 1);
> return true;
> /* vec_mergeh (integrals). */
> case RS6000_BIF_VMRGHH:
> case RS6000_BIF_VMRGHW:
> - case RS6000_BIF_XXMRGHW_4SI:
> case RS6000_BIF_VMRGHB:
> case RS6000_BIF_VEC_MERGEH_V2DI:
> - case RS6000_BIF_XXMRGHW_4SF:
> case RS6000_BIF_VEC_MERGEH_V2DF:
> fold_mergehl_helper (gsi, stmt, 0);
> return true;
> diff --git a/gcc/config/rs6000/rs6000-builtins.def
> b/gcc/config/rs6000/rs6000-builtins.def
> index 5b7237a2327..d09e21a9151 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -1904,18 +1904,6 @@
> const signed int __builtin_vsx_xvtsqrtsp_fg (vf);
> XVTSQRTSP_FG vsx_tsqrtv4sf2_fg {}
>
> - const vf __builtin_vsx_xxmrghw (vf, vf);
> - XXMRGHW_4SF vsx_xxmrghw_v4sf {}
> -
> - const vsi __builtin_vsx_xxmrghw_4si (vsi, vsi);
> - XXMRGHW_4SI vsx_xxmrghw_v4si {}
> -
> - const vf __builtin_vsx_xxmrglw (vf, vf);
> - XXMRGLW_4SF vsx_xxmrglw_v4sf {}
> -
> - const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi);
> - XXMRGLW_4SI vsx_xxmrglw_v4si {}
> -
> const vsc __builtin_vsx_xxpermdi_16qi (vsc, vsc, const int<2>);
> XXPERMDI_16QI vsx_xxpermdi_v16qi {}
>
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 3d39ae7995f..26560ecc38a 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -4810,47 +4810,6 @@
> }
> [(set_attr "type" "vecperm")])
>
> -;; V4SF/V4SI interleave
> -(define_expand "vsx_xxmrghw_<mode>"
> - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
> - (vec_select:VSX_W
> - (vec_concat:<VS_double>
> - (match_operand:VSX_W 1 "vsx_register_operand" "wa")
> - (match_operand:VSX_W 2 "vsx_register_operand" "wa"))
> - (parallel [(const_int 0) (const_int 4)
> - (const_int 1) (const_int 5)])))]
> - "VECTOR_MEM_VSX_P (<MODE>mode)"
> -{
> - rtx (*fun) (rtx, rtx, rtx);
> - fun = BYTES_BIG_ENDIAN ? gen_altivec_vmrghw_direct_<mode>
> - : gen_altivec_vmrglw_direct_<mode>;
> - if (!BYTES_BIG_ENDIAN)
> - std::swap (operands[1], operands[2]);
> - emit_insn (fun (operands[0], operands[1], operands[2]));
> - DONE;
> -}
> - [(set_attr "type" "vecperm")])
> -
> -(define_expand "vsx_xxmrglw_<mode>"
> - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
> - (vec_select:VSX_W
> - (vec_concat:<VS_double>
> - (match_operand:VSX_W 1 "vsx_register_operand" "wa")
> - (match_operand:VSX_W 2 "vsx_register_operand" "wa"))
> - (parallel [(const_int 2) (const_int 6)
> - (const_int 3) (const_int 7)])))]
> - "VECTOR_MEM_VSX_P (<MODE>mode)"
> -{
> - rtx (*fun) (rtx, rtx, rtx);
> - fun = BYTES_BIG_ENDIAN ? gen_altivec_vmrglw_direct_<mode>
> - : gen_altivec_vmrghw_direct_<mode>;
> - if (!BYTES_BIG_ENDIAN)
> - std::swap (operands[1], operands[2]);
> - emit_insn (fun (operands[0], operands[1], operands[2]));
> - DONE;
> -}
> - [(set_attr "type" "vecperm")])
> -
> ;; Shift left double by word immediate
> (define_insn "vsx_xxsldwi_<mode>"
> [(set (match_operand:VSX_L 0 "vsx_register_operand" "=wa")
