https://gcc.gnu.org/g:8c6ee63bcd653c736d4cabafcbfd4f62582391ff
commit r14-10082-g8c6ee63bcd653c736d4cabafcbfd4f62582391ff
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Tue Apr 23 00:17:49 2024 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 64 ++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/m2/ChangeLog | 19 ++++++++
gcc/testsuite/ChangeLog | 118 ++++++++++++++++++++++++++++++++++++++++++++++++
libstdc++-v3/ChangeLog | 32 +++++++++++++
5 files changed, 234 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2cec10b83c8..dd6d2c59eb6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,67 @@
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ * config/riscv/vector-crypto.md:
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ Revert:
+ 2023-11-30 Juzhe-Zhong <juzhe.zh...@rivai.ai>
+
+ * config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Fix
constraint.
+ * config/riscv/riscv.md (no,W21,W42,W84,W41,W81,W82): Rename
vconstraint into group_overlap.
+ (no,yes): Ditto.
+ (none,W21,W42,W84,W43,W86,W87): Ditto.
+ * config/riscv/vector.md: Ditto.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ Revert:
+ 2023-12-04 Juzhe-Zhong <juzhe.zh...@rivai.ai>
+
+ * config/riscv/riscv.md: Rostify the constraints.
+
+2024-04-22 Haochen Jiang <haochen.ji...@intel.com>
+
+ * common/config/i386/i386-common.cc (processor_alias_table):
+ Let Sierra Forest map to CPU_TYPE enum.
+
+2024-04-22 Andreas Krebbel <kreb...@linux.ibm.com>
+
+ * config/s390/s390.cc (s390_option_override_internal): Check zarch
+ flag before enabling -mvx.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ Revert:
+ 2023-11-30 Juzhe-Zhong <juzhe.zh...@rivai.ai>
+
+ PR target/112431
+ * config/riscv/vector.md: Add widenning overlap.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ Revert:
+ 2023-12-01 Juzhe-Zhong <juzhe.zh...@rivai.ai>
+
+ PR target/112431
+ * config/riscv/vector.md: Support highpart overlap for indexed load.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ Revert:
+ 2023-12-04 Juzhe-Zhong <juzhe.zh...@rivai.ai>
+
+ PR target/112431
+ * config/riscv/vector.md: Add highest-number overlap support.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ Revert:
+ 2023-11-30 Juzhe-Zhong <juzhe.zh...@rivai.ai>
+
+ PR target/112431
+ * config/riscv/vector.md: Add widening overlap of vf2/vf4.
+
2024-04-21 Pan Li <pan2...@intel.com>
Revert:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ae66f046552..f007dcf5a81 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240422
+20240423
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index 1ef9df9eac7..e4faadae366 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,22 @@
+2024-04-22 Gaius Mulley <gaiusm...@gmail.com>
+
+ PR modula2/114811
+ * gm2-compiler/M2GenGCC.mod (FoldBinarySet): Add condition
+ checking to ensure op2 and op3 are fully resolved before
+ type checking is performed.
+
+2024-04-22 Gaius Mulley <gaiusm...@gmail.com>
+
+ PR modula2/114807
+ * gm2-compiler/M2Check.mod (checkUnbounded): Remove unused
+ local variables.
+ (constCheckMeta): Include check for IsReallyPointer in the
+ failure case.
+ * gm2-compiler/M2Quads.mod (MoveWithMode): Remove CopyConstString.
+ * gm2-compiler/SymbolTable.def (IsHiddenReallyPointer): Export.
+ * gm2-compiler/SymbolTable.mod (SkipHiddenType): Remove.
+ (IsReallyPointer): Include IsHiddenReallyPointer test.
+
2024-04-20 Gaius Mulley <gaiusm...@gmail.com>
PR modula2/112893
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8d20f6aa3a4..e806065b1a3 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,121 @@
+2024-04-22 Gaius Mulley <gaiusm...@gmail.com>
+
+ PR modula2/114811
+ * lib/gm2-torture.exp: Correct regexp checking for internal
+ compiler error strings in compiler output.
+
+2024-04-22 Gaius Mulley <gaiusm...@gmail.com>
+
+ PR modula2/114807
+ * gm2/pim/fail/badproctype.mod: Change MYSHORTREAL
+ to SHORTREAL.
+ * gm2/pim/fail/badprocbool.mod: New test.
+ * gm2/pim/fail/badproccard.mod: New test.
+ * gm2/pim/fail/badprocint.mod: New test.
+ * gm2/pim/fail/badprocint2.mod: New test.
+ * gm2/pim/pass/goodproccard2.mod: New test.
+ * gm2/pim/pass/goodprocint.mod: New test.
+ * gm2/pim/pass/goodprocint3.mod: New test.
+ * gm2/pim/run/pass/genconststr.mod: New test.
+
+2024-04-22 Marek Polacek <pola...@redhat.com>
+
+ * lib/prune.exp (prune_gcc_output): Also prune -freport-bug output.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/base/pr112431-10.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-11.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-12.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-13.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-14.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-15.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-7.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-8.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-9.c: New test.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ Revert:
+ 2024-04-22 Juzhe-Zhong <juzhe.zh...@rivai.ai>
+
+ PR target/112431
+ * gcc.target/riscv/rvv/base/pr112431-10.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-11.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-12.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-13.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-14.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-15.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-7.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-8.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-9.c: New test.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/base/pr112431-34.c: Remove xfail for vluxei8
check.
+ * gcc.target/riscv/rvv/base/pr112431-28.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-29.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-30.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-31.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-32.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-33.c: New test.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ Revert:
+ 2024-04-22 Juzhe-Zhong <juzhe.zh...@rivai.ai>
+
+ PR target/112431
+ * gcc.target/riscv/rvv/base/pr112431-28.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-29.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-30.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-31.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-32.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-33.c: New test.
+
+2024-04-22 Stefan Schulze Frielinghaus <stefa...@linux.ibm.com>
+
+ * gcc.target/s390/vxe/popcount-1.c: Remove xfail.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/base/pr112431-37.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-38.c: New test.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ Revert:
+ 2024-04-22 Juzhe-Zhong <juzhe.zh...@rivai.ai>
+
+ PR target/112431
+ * gcc.target/riscv/rvv/base/pr112431-37.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-38.c: New test.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/base/pr112431-16.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-17.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-18.c: New test.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ Revert:
+ 2024-04-22 Juzhe-Zhong <juzhe.zh...@rivai.ai>
+
+ PR target/112431
+ * gcc.target/riscv/rvv/base/pr112431-16.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-17.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-18.c: New test.
+
+2024-04-22 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/base/pr112431-22.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-23.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-24.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-25.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-26.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-27.c: New test.
+
2024-04-21 Paul Thomas <pa...@gcc.gnu.org>
PR fortran/103471
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 98895ea9795..ce23e32ba99 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,35 @@
+2024-04-22 Matthias Kretz <m.kr...@gsi.de>
+
+ PR libstdc++/114803
+ * include/experimental/bits/simd_builtin.h
+ (_SimdBase2::operator __vector_type_t): There is no __builtin()
+ function in _SimdWrapper, instead use its conversion operator.
+ * testsuite/experimental/simd/pr114803_vecbuiltin_cvt.cc: New
+ test.
+
+2024-04-22 Matthias Kretz <m.kr...@gsi.de>
+
+ * include/experimental/bits/simd.h: Ignore -Wnarrowing for
+ arm_neon.h.
+ (__int_for_sizeof): Replace tautological compare with checking
+ for invalid template parameter value.
+ * include/experimental/bits/simd_builtin.h (__extract_part):
+ Remove tautological compare by combining two static_assert.
+
+2024-04-22 Jakub Jelinek <ja...@redhat.com>
+
+ * testsuite/17_intro/names.cc (d, f): Undefine on s390*-linux*.
+ * testsuite/17_intro/headers/c++1998/all_attributes.cc (packed): Don't
+ define on s390.
+ * testsuite/17_intro/headers/c++2011/all_attributes.cc (packed):
+ Likewise.
+ * testsuite/17_intro/headers/c++2014/all_attributes.cc (packed):
+ Likewise.
+ * testsuite/17_intro/headers/c++2017/all_attributes.cc (packed):
+ Likewise.
+ * testsuite/17_intro/headers/c++2020/all_attributes.cc (packed):
+ Likewise.
+
2024-04-19 Jonathan Wakely <jwak...@redhat.com>
* include/bits/refwrap.h (operator<=>): Simplify constraints.
