Colleagues:
I am a software professional with very liittle VHDL experience. I need
some guidance on how to debug VHDL and/or GHDL compiler issues.
I am attempting to simulate a test driver for the DDR DRAM on the
Spartan 3E starter kit. I downloaded the old package from
http://www.xdr.com/dash/fpga/
And modified it for Xilinx ISE 11.1 in my environment.
I compiled and ran the project with GHDL, but the DCM did not generate
the expected 2x clock: all the DCM output clocks remained
flat.
Further investigation shows that this was reported on the Xilinx
forum: DCM fails to lock for GHDL but locks for Modelsim, for newer
ISE versions.
Within the Xilinx unisim DCM.vhd, the code was changed in 2008 and
there now a generic called SIM_MODE. I set SIM_MIDE="FAST"
and instead of a failure to lock, I got a GHDL runtime error. The
runtime error output is:
../../../src/std/textio_body.v93:1018:5:@0ms:(assertion failure): real
read failure
./mytb:error: assertion failed
./mytb:error: simulation failed
ghdl: compilation error
I began using classical brute-force software debugging techniques: I
simplified the VDHL down to a single instantiation of the DCM in a
single VHDL module, with the same results, namely failure to lock with
SIM_MODE defaulted and the error with SIM_MODE="FAST"
I made a local copy of DCM.vhd and changed the entity name: same results.
I intend to now continue to fault isolate by simplifying DCM.vhd.
Now for my questions:
1) is there a simpler way?
2) is this a GHDL problem or a problem with the Xilinx unisim?
My environment is 64-bit Gentoo Linux.
Thanks
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