On Thu, 05 Nov 2015, Rodrigo Vivi <rodrigo.v...@intel.com> wrote:
> Since the beginning there is a confusion on the meaning of this bit.
>
> A previous patch had identified this already and fixed it partially:
> 'commit 3301d409 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic")
>
> DP_PSR_NO_TRAIN_ON_EXIT means the source doesn't need to do the
> training, but it doesn't tell to avoid TP patterns or to skip
> aux handshake.
>
> This patch fixes the hard freeze reported.
>
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91436
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91437
>
> Cc: Ivan Mitev <ivan.mi...@gmail.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>I'm unhappy about mixing fixes like this in 30+ patch series. Jani. > --- > drivers/gpu/drm/i915/intel_psr.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index c090f38..4e88e2e 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -263,7 +263,6 @@ static void hsw_psr_enable_source(struct intel_dp > *intel_dp) > send the minimal TP1 possible and skip TP2. */ > val |= EDP_PSR_TP1_TIME_100us; > val |= EDP_PSR_TP2_TP3_TIME_0us; > - val |= EDP_PSR_SKIP_AUX_EXIT; > /* Sink should be able to train with the 5 or 6 idle patterns */ > idle_frames += 4; > } -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
