On Wed, Nov 04, 2015 at 05:41:16PM +0200, Ander Conselvan De Oliveira wrote:
> Reviewed-by: Ander Conselvan de Oliveira <conselv...@gmail.com>
Pushed to dinq. Thanks for the review.
> On Fri, 2015-10-30 at 23:39 +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> >
> > Currently there's no trace in dmesg when the gen2/3 dotclock checks
> > reject the modeset. Add some to avoid further head scratching.
> >
> > While at it refactor the code a bit to look nicer.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++--------
> > 1 file changed, 18 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 2b70151..1509a99 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6599,6 +6599,15 @@ static void hsw_compute_ips_config(struct intel_crtc
> > *crtc,
> > pipe_config_supports_ips(dev_priv, pipe_config);
> > }
> >
> > +static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
> > +{
> > + const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +
> > + /* GDG double wide on either pipe, otherwise pipe A only */
> > + return INTEL_INFO(dev_priv)->gen < 4 &&
> > + (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
> > +}
> > +
> > static int intel_crtc_compute_config(struct intel_crtc *crtc,
> > struct intel_crtc_state *pipe_config)
> > {
> > @@ -6608,23 +6617,24 @@ static int intel_crtc_compute_config(struct
> > intel_crtc
> > *crtc,
> >
> > /* FIXME should check pixel clock limits on all platforms */
> > if (INTEL_INFO(dev)->gen < 4) {
> > - int clock_limit = dev_priv->max_cdclk_freq;
> > + int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
> >
> > /*
> > - * Enable pixel doubling when the dot clock
> > + * Enable double wide mode when the dot clock
> > * is > 90% of the (display) core speed.
> > - *
> > - * GDG double wide on either pipe,
> > - * otherwise pipe A only.
> > */
> > - if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
> > - adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
> > + if (intel_crtc_supports_double_wide(crtc) &&
> > + adjusted_mode->crtc_clock > clock_limit) {
> > clock_limit *= 2;
> > pipe_config->double_wide = true;
> > }
> >
> > - if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
> > + if (adjusted_mode->crtc_clock > clock_limit) {
> > + DRM_DEBUG_KMS("requested pixel clock (%d kHz) too
> > high (max: %d kHz, double wide: %s)\n",
> > + adjusted_mode->crtc_clock, clock_limit,
> > + yesno(pipe_config->double_wide));
> > return -EINVAL;
> > + }
> > }
> >
> > /*
--
Ville Syrjälä
Intel OTC
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