On Fri, Nov 10, 2017 at 2:09 PM, Dave Hansen
<dave.han...@linux.intel.com> wrote:
> On 11/10/2017 02:03 PM, Andy Lutomirski wrote:
>>> +static inline u16 kern_asid(u16 asid)
>>> +{
>>> + VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
>>> + /*
>>> + * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID
>>> + * bits. This serves two purposes. It prevents a nasty situation
>>> in
>>> + * which PCID-unaware code saves CR3, loads some other value (with
>>> PCID
>>> + * == 0), and then restores CR3, thus corrupting the TLB for ASID 0
>>> if
>>> + * the saved ASID was nonzero. It also means that any bugs
>>> involving
>>> + * loading a PCID-enabled CR3 with CR4.PCIDE off will trigger
>>> + * deterministically.
>>> + */
>>> + return asid + 1;
>>> +}
>> This seems really error-prone. Maybe we should have a pcid_t type and
>> make all the interfaces that want a h/w PCID take pcid_t.
>
> Yeah, totally agree. I actually had a nasty bug or two around this area
> because of this.
>
> I divided them among hw_asid_t and sw_asid_t. You can turn a sw_asid_t
> into a kernel hw_asid_t or a user hw_asid_t. But, it cause too much
> churn across the TLB flushing code so I shelved it for now.
>
> I'd love to come back nd fix this up properly though.
In the long run, I would go with int for the sw asid and pcid_t for
the PCID. After all, we index arrays with the SW one.
