The following commit has been merged into the perf/core branch of tip: Commit-ID: 3cb9d5464c1ceea86f6225089b2f7965989cf316 Gitweb: https://git.kernel.org/tip/3cb9d5464c1ceea86f6225089b2f7965989cf316 Author: Wei Wang <wei.w.w...@intel.com> AuthorDate: Sat, 13 Jun 2020 16:09:46 +08:00 Committer: Peter Zijlstra <pet...@infradead.org> CommitterDate: Thu, 02 Jul 2020 15:51:45 +02:00
perf/x86: Fix variable types for LBR registers The MSR variable type can be 'unsigned int', which uses less memory than the longer 'unsigned long'. Fix 'struct x86_pmu' for that. The lbr_nr won't be a negative number, so make it 'unsigned int' as well. Suggested-by: Peter Zijlstra (Intel) <pet...@infradead.org> Signed-off-by: Wei Wang <wei.w.w...@intel.com> Signed-off-by: Peter Zijlstra (Intel) <pet...@infradead.org> Link: https://lkml.kernel.org/r/20200613080958.132489-2-like...@linux.intel.com --- arch/x86/events/perf_event.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index e17a3d8..eb37f6c 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -673,8 +673,8 @@ struct x86_pmu { /* * Intel LBR */ - unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ - int lbr_nr; /* hardware stack size */ + unsigned int lbr_tos, lbr_from, lbr_to, + lbr_nr; /* LBR base regs and size */ u64 lbr_sel_mask; /* LBR_SELECT valid bits */ const int *lbr_sel_map; /* lbr_select mappings */ bool lbr_double_abort; /* duplicated lbr aborts */
