Enabled MHI device support over PCIe and added memory
reservation required for MHI enabled QCN9000 PCIe card.
Signed-off-by: Gokul Sriram Palanisamy <gokul...@codeaurora.org>
Reported-by: kbuild test robot <l...@intel.com>
---
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 46 ++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
index 0827055..1bbce2d 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
@@ -24,6 +24,22 @@
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x20000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ qcn9000_pcie0: memory@50f00000 {
+ no-map;
+ reg = <0x0 0x50f00000 0x0 0x03700000>;
+ };
+
+ qcn9000_pcie1: memory@54600000 {
+ no-map;
+ reg = <0x0 0x54600000 0x0 0x03700000>;
+ };
+ };
};
&blsp1_spi1 {
@@ -45,11 +61,41 @@
&pcie0 {
status = "ok";
perst-gpio = <&tlmm 58 0x1>;
+
+ pcie0_rp: pcie0_rp {
+ reg = <0 0 0 0 0>;
+
+ status = "ok";
+ mhi_0: qcom,mhi@0 {
+ reg = <0 0 0 0 0 >;
+
+ qrtr_instance_id = <0x20>;
+ base-addr = <0x50f00000>;
+ m3-dump-addr = <0x53c00000>;
+ etr-addr = <0x53d00000>;
+ qcom,caldb-addr = <0x53e00000>;
+ };
+ };
};
&pcie1 {
status = "ok";
perst-gpio = <&tlmm 61 0x1>;
+
+ pcie1_rp: pcie1_rp {
+ reg = <0 0 0 0 0>;
+
+ status = "ok";
+ mhi_1: qcom,mhi@1 {
+ reg = <0 0 0 0 0 >;
+
+ qrtr_instance_id = <0x21>;
+ base-addr = <0x54600000>;
+ m3-dump-addr = <0x57300000>;
+ etr-addr = <0x57400000>;
+ qcom,caldb-addr = <0x57500000>;
+ };
+ };
};
&qmp_pcie_phy0 {
--
2.7.4
