On 8/15/21 2:27 AM, Mike Rapoport wrote:
On Thu, Aug 12, 2021 at 04:37:35PM -0700, Vineet Gupta wrote:
MMU SCRATCH_DATA0 register is intended to cache task pgd. However in
ARC700 SMP port, it has to be repurposed for reentrant interrupt
handling, while UP port doesn't. We currently ahandle boe usecases
^ handle both
maybe ':set spell' for changelog editing? ;-)
Seriously, about time I stopped fat-fingering
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