Nicholas Piggin <npig...@gmail.com> writes: > The most expensive ordering for hwsync to provide is the store-load > barrier, because all prior stores have to be drained to the caches > before subsequent instructions can complete. > > stsync just orders stores which means it can just be a barrer that > goes down the store queue and orders draining, and does not prevent > completion of subsequent instructions. So it should be faster than > hwsync. > > Use stsync for wmb(). Older processors that don't recognise the SC > field should treat this as hwsync.
qemu (7.1) emulating ppc64e does not :/ mpic: Setting up MPIC " OpenPIC " version 1.2 at fe0040000, max 1 CPUs mpic: ISU size: 256, shift: 8, mask: ff mpic: Initializing for 256 sources Oops: Exception in kernel mode, sig: 4 [#1] No more output. (qemu) info registers │ NIP c000000000df4264 LR c0000000000ce49c CTR 0000000000000000 XER 0000000020000000 CPU#0 │ MSR 0000000080001000 HID0 0000000000000000 HF 24020006 iidx 1 didx 1 │ ... SRR0 c0000000000ce7c4 SRR1 0000000080081000 PVR 0000000080240020 VRSAVE 0000000000000000 $ objdump -d vmlinux | grep c0000000000ce7c4 c0000000000ce7c4: 7c 03 04 ac stsync That's qemu -M ppce500 -cpu e5500 or e6500. I guess just put it behind an #ifdef 64S. cheers