On Mon, Feb 05, 2024 at 01:30:46PM +1100, Benjamin Gray wrote: > On Thu, 2023-11-30 at 15:55 +0530, Naveen N Rao wrote: > > On Mon, Oct 16, 2023 at 04:01:45PM +1100, Benjamin Gray wrote: > > > > > > diff --git a/arch/powerpc/include/asm/code-patching.h > > > b/arch/powerpc/include/asm/code-patching.h > > > index 3f881548fb61..7c6056bb1706 100644 > > > --- a/arch/powerpc/include/asm/code-patching.h > > > +++ b/arch/powerpc/include/asm/code-patching.h > > > @@ -75,6 +75,39 @@ int patch_branch(u32 *addr, unsigned long > > > target, int flags); > > > int patch_instruction(u32 *addr, ppc_inst_t instr); > > > int raw_patch_instruction(u32 *addr, ppc_inst_t instr); > > > > > > +/* > > > + * patch_uint() and patch_ulong() should only be called on > > > addresses where the > > > + * patch does not cross a cacheline, otherwise it may not be > > > flushed properly > > > + * and mixes of new and stale data may be observed. It cannot > > > cross a page > > > + * boundary, as only the target page is mapped as writable. > > > > Should we enforce alignment requirements, especially for > > patch_ulong() > > on 64-bit powerpc? I am not sure if there are use cases for unaligned > > 64-bit writes. That should also ensure that the write doesn't cross a > > cacheline. > > Yeah, the current description is more just the technical restrictions, > not an endorsement of usage. If the caller isn't working with aligned > data, it seems unlikely it would still be cacheline aligned. The caller > should break it into 32bit patches if this is the case. > > By enforce, are you suggesting a WARN_ON in the code too?
No, just detecting and returning an error code should help detect incorrect usage. - Naveen