================ @@ -65,10 +65,27 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { VentanaVeyron, }; // clang-format on + + enum RISCVProfileEnum : uint8_t { + Unspecified, + RVI20U32, + RVI20U64, + RVA20U64, + RVA20S64, + RVA22U64, + RVA22S64, + RVA23U64, + RVA23S64, + RVB23U64, + RVB23S64, + RVM23U32, + }; + private: virtual void anchor(); RISCVProcFamilyEnum RISCVProcFamily = Others; + RISCVProfileEnum RISCVProfile = Unspecified; ---------------- kito-cheng wrote:
Same https://github.com/llvm/llvm-project/pull/84877 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits