https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/84877
>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng...@bytedance.com>
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
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Content-Type: text/plain; charset=UTF-8
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Created using spr 1.3.4
---
clang/test/Driver/riscv-cpus.c | 319 ++++++++++++++++++++++
clang/test/Misc/target-invalid-cpu-note.c | 8 +-
llvm/lib/Target/RISCV/RISCVProcessors.td | 224 ++++++++++++++-
3 files changed, 539 insertions(+), 12 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..a285f0f9c41f54 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -302,3 +302,322 @@
// RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
// MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// Check profile CPUs
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 |
FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s
+// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 |
FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s
+// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 |
FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s
+// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 |
FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s
+// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 |
FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s
+// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicboz"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zihpm"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+za64rs"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zfhmin"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zkt"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22s64 |
FileCheck -check-prefix=MCPU-GENERIC-RVA22S64 %s
+// MCPU-GENERIC-RVA22S64: "-target-cpu" "generic-rva22s64"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicboz"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zihpm"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+za64rs"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zfhmin"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zkt"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+sscounterenw"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svinval"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svpbmt"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva23u64
-menable-experimental-extensions \
+// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVA23U64 %s
+// MCPU-GENERIC-RVA23U64: "-target-cpu" "generic-rva23u64"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+v"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicboz"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicond"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zihintntl"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zihpm"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+za64rs"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zawrs"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zfa"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zfhmin"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zcb"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zkt"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zvbb"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zvfhmin"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zvkt"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva23s64
-menable-experimental-extensions \
+// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVA23S64 %s
+// MCPU-GENERIC-RVA23S64: "-target-cpu" "generic-rva23s64"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+v"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+h"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicboz"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicond"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zihintntl"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zihpm"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+za64rs"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zawrs"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zfa"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zfhmin"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zcb"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zkt"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zvbb"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zvfhmin"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zvkt"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shcounterenw"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shgatpa"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shtvala"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shvsatpa"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shvstvala"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shvstvecd"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sscofpmf"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sscounterenw"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+experimental-ssnpm"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ssstateen"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sstc"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ssu64xl"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svinval"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svnapot"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svpbmt"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvb23u64
-menable-experimental-extensions \
+// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVB23U64 %s
+// MCPU-GENERIC-RVB23U64: "-target-cpu" "generic-rvb23u64"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicboz"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicond"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zihintntl"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zihpm"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+za64rs"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zawrs"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zfa"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zcb"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zkt"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvb23s64
-menable-experimental-extensions \
+// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVB23S64 %s
+// MCPU-GENERIC-RVB23S64: "-target-cpu" "generic-rvb23s64"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicboz"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicond"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zihintntl"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zihpm"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+za64rs"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zawrs"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zfa"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zcb"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zkt"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sscofpmf"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sscounterenw"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sstc"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ssu64xl"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svinval"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svnapot"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svpbmt"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvm23u32
-menable-experimental-extensions \
+// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVM23U32 %s
+// MCPU-GENERIC-RVM23U32: "-target-cpu" "generic-rvm23u32"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zicond"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zihintntl"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zce"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-abi" "ilp32"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index b65a8fb057ee53..41347f9ed7aa14 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -81,16 +81,16 @@
// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV32
// RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32,
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76,
syntacore-scr1-base, syntacore-scr1-max{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: generic-rv32,
generic-rvi20u32, generic-rvm23u32, rocket-rv32, sifive-e20, sifive-e21,
sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base,
syntacore-scr1-max{{$}}
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
generic-rva20s64, generic-rva20u64, generic-rva22s64, generic-rva22u64,
generic-rva23s64, generic-rva23u64, generic-rvb23s64, generic-rvb23u64,
generic-rvi20u64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21,
sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280,
veyron-v1, xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32,
rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34,
sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket,
sifive-7-series{{$}}
+// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32,
generic-rvi20u32, generic-rvm23u32, rocket-rv32, sifive-e20, sifive-e21,
sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base,
syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu,
generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
generic-rva20s64, generic-rva20u64, generic-rva22s64, generic-rva22u64,
generic-rva23s64, generic-rva23u64, generic-rvb23s64, generic-rvb23u64,
generic-rvi20u64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21,
sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280,
veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 8c75df41f5e395..9c0ca06de0a5a8 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -10,6 +10,179 @@
// RISC-V processors supported.
//===----------------------------------------------------------------------===//
+defvar RVA20U64Features = [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZicntr,
+ FeatureStdExtZiccif,
+ FeatureStdExtZiccrse,
+ FeatureStdExtZiccamoa,
+ FeatureStdExtZa128rs,
+ FeatureStdExtZicclsm];
+
+defvar RVA20S64Features = !listconcat(RVA20U64Features,
+ [FeatureStdExtZifencei,
+ FeatureStdExtSvbare,
+ FeatureStdExtSvade,
+ FeatureStdExtSsccptr,
+ FeatureStdExtSstvecd,
+ FeatureStdExtSstvala]);
+
+defvar RVA22U64Features = [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZicntr,
+ FeatureStdExtZiccif,
+ FeatureStdExtZiccrse,
+ FeatureStdExtZiccamoa,
+ FeatureStdExtZicclsm,
+ FeatureStdExtZa64rs,
+ FeatureStdExtZihpm,
+ FeatureStdExtZihintpause,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZic64b,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicbop,
+ FeatureStdExtZicboz,
+ FeatureStdExtZfhmin,
+ FeatureStdExtZkt];
+
+defvar RVA22S64Features = !listconcat(RVA22U64Features,
+ [FeatureStdExtZifencei,
+ FeatureStdExtSvbare,
+ FeatureStdExtSvade,
+ FeatureStdExtSsccptr,
+ FeatureStdExtSstvecd,
+ FeatureStdExtSstvala,
+ FeatureStdExtSscounterenw,
+ FeatureStdExtSvpbmt,
+ FeatureStdExtSvinval]);
+
+defvar RVA23U64Features = [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZicntr,
+ FeatureStdExtZihpm,
+ FeatureStdExtZiccif,
+ FeatureStdExtZiccrse,
+ FeatureStdExtZiccamoa,
+ FeatureStdExtZicclsm,
+ FeatureStdExtZa64rs,
+ FeatureStdExtZihintpause,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZic64b,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicbop,
+ FeatureStdExtZicboz,
+ FeatureStdExtZfhmin,
+ FeatureStdExtZkt,
+ FeatureStdExtV,
+ FeatureStdExtZvfhmin,
+ FeatureStdExtZvbb,
+ FeatureStdExtZvkt,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZicond,
+ FeatureStdExtZimop,
+ FeatureStdExtZcmop,
+ FeatureStdExtZcb,
+ FeatureStdExtZfa,
+ FeatureStdExtZawrs];
+
+defvar RVA23S64Features = !listconcat(RVA23U64Features,
+ [FeatureStdExtZifencei,
+ FeatureStdExtSvbare,
+ FeatureStdExtSvade,
+ FeatureStdExtSsccptr,
+ FeatureStdExtSstvecd,
+ FeatureStdExtSstvala,
+ FeatureStdExtSscounterenw,
+ FeatureStdExtSvpbmt,
+ FeatureStdExtSvinval,
+ FeatureStdExtSvnapot,
+ FeatureStdExtSstc,
+ FeatureStdExtSscofpmf,
+ FeatureStdExtSsnpm,
+ FeatureStdExtSsu64xl,
+ FeatureStdExtH,
+ FeatureStdExtSsstateen,
+ FeatureStdExtShcounterenw,
+ FeatureStdExtShvstvala,
+ FeatureStdExtShtvala,
+ FeatureStdExtShvstvecd,
+ FeatureStdExtShvsatpa,
+ FeatureStdExtShgatpa]);
+
+defvar RVB23U64Features = [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZicntr,
+ FeatureStdExtZihpm,
+ FeatureStdExtZiccif,
+ FeatureStdExtZiccrse,
+ FeatureStdExtZiccamoa,
+ FeatureStdExtZicclsm,
+ FeatureStdExtZa64rs,
+ FeatureStdExtZihintpause,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZic64b,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicbop,
+ FeatureStdExtZicboz,
+ FeatureStdExtZkt,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZicond,
+ FeatureStdExtZimop,
+ FeatureStdExtZcmop,
+ FeatureStdExtZcb,
+ FeatureStdExtZfa,
+ FeatureStdExtZawrs];
+
+defvar RVB23S64Features = !listconcat(RVB23U64Features,
+ [FeatureStdExtZifencei,
+ FeatureStdExtSvnapot,
+ FeatureStdExtSvbare,
+ FeatureStdExtSvade,
+ FeatureStdExtSsccptr,
+ FeatureStdExtSstvecd,
+ FeatureStdExtSstvala,
+ FeatureStdExtSscounterenw,
+ FeatureStdExtSvpbmt,
+ FeatureStdExtSvinval,
+ FeatureStdExtSstc,
+ FeatureStdExtSscofpmf,
+ FeatureStdExtSsu64xl]);
+
+defvar RVM23U32Features = [Feature32Bit,
+ FeatureStdExtM,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZicond,
+ FeatureStdExtZihintpause,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZce,
+ FeatureStdExtZicbop,
+ FeatureStdExtZimop,
+ FeatureStdExtZcmop];
+
class RISCVTuneInfo {
bits<8> PrefFunctionAlignment = 1;
bits<8> PrefLoopAlignment = 1;
@@ -54,14 +227,49 @@ class RISCVTuneProcessorModel<string n,
list<SubtargetFeature> f = []>
: ProcessorModel<n, m, f,tunef>;
-def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
- NoSchedModel,
- [Feature32Bit]>,
- GenericTuneInfo;
-def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
- NoSchedModel,
- [Feature64Bit]>,
- GenericTuneInfo;
+class RISCVGenericProcessorModel<string n, list<SubtargetFeature> f>
+ : RISCVProcessorModel<n, NoSchedModel, f>,
+ GenericTuneInfo;
+
+def GENERIC_RV32 : RISCVGenericProcessorModel<"generic-rv32",
+ [Feature32Bit]>;
+
+def GENERIC_RV64 : RISCVGenericProcessorModel<"generic-rv64",
+ [Feature64Bit]>;
+
+def GENERIC_RVI20U32 : RISCVGenericProcessorModel<"generic-rvi20u32",
+ [Feature32Bit]>;
+
+def GENERIC_RVI20U64 : RISCVGenericProcessorModel<"generic-rvi20u64",
+ [Feature64Bit]>;
+
+def GENERIC_RVA20U64 : RISCVGenericProcessorModel<"generic-rva20u64",
+ RVA20U64Features>;
+
+def GENERIC_RVA20S64 : RISCVGenericProcessorModel<"generic-rva20s64",
+ RVA20S64Features>;
+
+def GENERIC_RVA22U64 : RISCVGenericProcessorModel<"generic-rva22u64",
+ RVA22U64Features>;
+
+def GENERIC_RVA22S64 : RISCVGenericProcessorModel<"generic-rva22s64",
+ RVA22S64Features>;
+
+def GENERIC_RVA23U64 : RISCVGenericProcessorModel<"generic-rva23u64",
+ RVA23U64Features>;
+
+def GENERIC_RVA23S64 : RISCVGenericProcessorModel<"generic-rva23s64",
+ RVA23S64Features>;
+
+def GENERIC_RVB23U64 : RISCVGenericProcessorModel<"generic-rvb23u64",
+ RVB23U64Features>;
+
+def GENERIC_RVB23S64 : RISCVGenericProcessorModel<"generic-rvb23s64",
+ RVB23S64Features>;
+
+def GENERIC_RVM23U32 : RISCVGenericProcessorModel<"generic-rvm23u32",
+ RVM23U32Features>;
+
// Support generic for compatibility with other targets. The triple will be
used
// to change to the appropriate rv32/rv64 version.
def : ProcessorModel<"generic", NoSchedModel, []>, GenericTuneInfo;
>From dc37018363c1dd00e269fccec1322e707add0218 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng...@bytedance.com>
Date: Mon, 25 Mar 2024 11:43:29 +0800
Subject: [PATCH 2/7] Remove genenic prefix
Created using spr 1.3.4
---
clang/test/Driver/riscv-cpus.c | 632 +++++++++++-----------
clang/test/Misc/target-invalid-cpu-note.c | 8 +-
llvm/lib/Target/RISCV/RISCVProcessors.td | 22 +-
3 files changed, 331 insertions(+), 331 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index a285f0f9c41f54..f65307f0ae50ae 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -305,319 +305,319 @@
// Check profile CPUs
-// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 |
FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s
-// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32"
-// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a"
-// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c"
-// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d"
-// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f"
-// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m"
-// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32"
-
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 |
FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s
-// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64"
-// MCPU-GENERIC-RVI20U64: "-target-feature" "-a"
-// MCPU-GENERIC-RVI20U64: "-target-feature" "-c"
-// MCPU-GENERIC-RVI20U64: "-target-feature" "-d"
-// MCPU-GENERIC-RVI20U64: "-target-feature" "-f"
-// MCPU-GENERIC-RVI20U64: "-target-feature" "-m"
-// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64"
-
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 |
FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s
-// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64"
-// MCPU-GENERIC-RVA20U64: "-target-feature" "+m"
-// MCPU-GENERIC-RVA20U64: "-target-feature" "+a"
-// MCPU-GENERIC-RVA20U64: "-target-feature" "+f"
-// MCPU-GENERIC-RVA20U64: "-target-feature" "+d"
-// MCPU-GENERIC-RVA20U64: "-target-feature" "+c"
-// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa"
-// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif"
-// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm"
-// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse"
-// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr"
-// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr"
-// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs"
-// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d"
-
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 |
FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s
-// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare"
-// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d"
-
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 |
FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s
-// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicboz"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+ziccamoa"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+ziccif"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicclsm"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+ziccrse"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicntr"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicsr"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zihintpause"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zihpm"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+za64rs"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zfhmin"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zba"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zbb"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zbs"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zkt"
-// MCPU-GENERIC-RVA22U64-SAME: "-target-abi" "lp64d"
-
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22s64 |
FileCheck -check-prefix=MCPU-GENERIC-RVA22S64 %s
-// MCPU-GENERIC-RVA22S64: "-target-cpu" "generic-rva22s64"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+m"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+a"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+f"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+d"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+c"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zic64b"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicbom"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicbop"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicboz"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ziccamoa"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ziccif"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicclsm"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ziccrse"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicntr"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicsr"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zifencei"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zihintpause"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zihpm"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+za64rs"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zfhmin"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zba"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zbb"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zbs"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zkt"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ssccptr"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+sscounterenw"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+sstvala"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+sstvecd"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svade"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svbare"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svinval"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svpbmt"
-// MCPU-GENERIC-RVA22S64-SAME: "-target-abi" "lp64d"
-
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva23u64
-menable-experimental-extensions \
-// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVA23U64 %s
-// MCPU-GENERIC-RVA23U64: "-target-cpu" "generic-rva23u64"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+m"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+a"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+f"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+d"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+c"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+v"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zic64b"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicbom"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicbop"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicboz"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+ziccamoa"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+ziccif"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicclsm"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+ziccrse"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicntr"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicond"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicsr"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zihintntl"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zihintpause"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zihpm"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+experimental-zimop"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+za64rs"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zawrs"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zfa"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zfhmin"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zcb"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+experimental-zcmop"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zba"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zbb"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zbs"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zkt"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zvbb"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zvfhmin"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zvkt"
-// MCPU-GENERIC-RVA23U64-SAME: "-target-abi" "lp64d"
-
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva23s64
-menable-experimental-extensions \
-// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVA23S64 %s
-// MCPU-GENERIC-RVA23S64: "-target-cpu" "generic-rva23s64"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+m"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+a"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+f"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+d"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+c"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+v"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+h"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zic64b"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicbom"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicbop"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicboz"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ziccamoa"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ziccif"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicclsm"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ziccrse"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicntr"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicond"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicsr"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zifencei"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zihintntl"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zihintpause"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zihpm"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+experimental-zimop"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+za64rs"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zawrs"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zfa"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zfhmin"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zcb"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+experimental-zcmop"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zba"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zbb"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zbs"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zkt"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zvbb"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zvfhmin"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zvkt"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shcounterenw"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shgatpa"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shtvala"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shvsatpa"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shvstvala"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shvstvecd"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ssccptr"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sscofpmf"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sscounterenw"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+experimental-ssnpm"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ssstateen"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sstc"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sstvala"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sstvecd"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ssu64xl"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svade"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svbare"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svinval"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svnapot"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svpbmt"
-// MCPU-GENERIC-RVA23S64-SAME: "-target-abi" "lp64d"
-
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvb23u64
-menable-experimental-extensions \
-// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVB23U64 %s
-// MCPU-GENERIC-RVB23U64: "-target-cpu" "generic-rvb23u64"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+m"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+a"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+f"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+d"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+c"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zic64b"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicbom"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicbop"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicboz"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+ziccamoa"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+ziccif"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicclsm"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+ziccrse"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicntr"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicond"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicsr"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zihintntl"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zihintpause"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zihpm"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+experimental-zimop"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+za64rs"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zawrs"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zfa"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zcb"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+experimental-zcmop"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zba"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zbb"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zbs"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zkt"
-// MCPU-GENERIC-RVB23U64-SAME: "-target-abi" "lp64d"
-
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvb23s64
-menable-experimental-extensions \
-// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVB23S64 %s
-// MCPU-GENERIC-RVB23S64: "-target-cpu" "generic-rvb23s64"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+m"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+a"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+f"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+d"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+c"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zic64b"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicbom"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicbop"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicboz"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ziccamoa"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ziccif"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicclsm"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ziccrse"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicntr"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicond"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicsr"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zifencei"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zihintntl"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zihintpause"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zihpm"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+experimental-zimop"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+za64rs"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zawrs"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zfa"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zcb"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+experimental-zcmop"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zba"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zbb"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zbs"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zkt"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ssccptr"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sscofpmf"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sscounterenw"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sstc"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sstvala"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sstvecd"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ssu64xl"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svade"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svbare"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svinval"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svnapot"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svpbmt"
-// MCPU-GENERIC-RVB23S64-SAME: "-target-abi" "lp64d"
-
-// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvm23u32
-menable-experimental-extensions \
-// RUN: | FileCheck -check-prefix=MCPU-GENERIC-RVM23U32 %s
-// MCPU-GENERIC-RVM23U32: "-target-cpu" "generic-rvm23u32"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+m"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zicbop"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zicond"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zicsr"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zihintntl"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zihintpause"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+experimental-zimop"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zce"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+experimental-zcmop"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zba"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zbb"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zbs"
-// MCPU-GENERIC-RVM23U32-SAME: "-target-abi" "ilp32"
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rvi20u32 | FileCheck
-check-prefix=MCPU-RVI20U32 %s
+// MCPU-RVI20U32: "-target-cpu" "rvi20u32"
+// MCPU-RVI20U32-SAME: "-target-feature" "-a"
+// MCPU-RVI20U32-SAME: "-target-feature" "-c"
+// MCPU-RVI20U32-SAME: "-target-feature" "-d"
+// MCPU-RVI20U32-SAME: "-target-feature" "-f"
+// MCPU-RVI20U32-SAME: "-target-feature" "-m"
+// MCPU-RVI20U32-SAME: "-target-abi" "ilp32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rvi20u64 | FileCheck
-check-prefix=MCPU-RVI20U64 %s
+// MCPU-RVI20U64: "-target-cpu" "rvi20u64"
+// MCPU-RVI20U64: "-target-feature" "-a"
+// MCPU-RVI20U64: "-target-feature" "-c"
+// MCPU-RVI20U64: "-target-feature" "-d"
+// MCPU-RVI20U64: "-target-feature" "-f"
+// MCPU-RVI20U64: "-target-feature" "-m"
+// MCPU-RVI20U64-SAME: "-target-abi" "lp64"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rva20u64 | FileCheck
-check-prefix=MCPU-RVA20U64 %s
+// MCPU-RVA20U64: "-target-cpu" "rva20u64"
+// MCPU-RVA20U64: "-target-feature" "+m"
+// MCPU-RVA20U64: "-target-feature" "+a"
+// MCPU-RVA20U64: "-target-feature" "+f"
+// MCPU-RVA20U64: "-target-feature" "+d"
+// MCPU-RVA20U64: "-target-feature" "+c"
+// MCPU-RVA20U64: "-target-feature" "+ziccamoa"
+// MCPU-RVA20U64: "-target-feature" "+ziccif"
+// MCPU-RVA20U64: "-target-feature" "+zicclsm"
+// MCPU-RVA20U64: "-target-feature" "+ziccrse"
+// MCPU-RVA20U64: "-target-feature" "+zicntr"
+// MCPU-RVA20U64: "-target-feature" "+zicsr"
+// MCPU-RVA20U64: "-target-feature" "+za128rs"
+// MCPU-RVA20U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rva20s64 | FileCheck
-check-prefix=MCPU-RVA20S64 %s
+// MCPU-RVA20S64: "-target-cpu" "rva20s64"
+// MCPU-RVA20S64-SAME: "-target-feature" "+m"
+// MCPU-RVA20S64-SAME: "-target-feature" "+a"
+// MCPU-RVA20S64-SAME: "-target-feature" "+f"
+// MCPU-RVA20S64-SAME: "-target-feature" "+d"
+// MCPU-RVA20S64-SAME: "-target-feature" "+c"
+// MCPU-RVA20S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-RVA20S64-SAME: "-target-feature" "+ziccif"
+// MCPU-RVA20S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-RVA20S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-RVA20S64-SAME: "-target-feature" "+zicntr"
+// MCPU-RVA20S64-SAME: "-target-feature" "+zicsr"
+// MCPU-RVA20S64-SAME: "-target-feature" "+zifencei"
+// MCPU-RVA20S64-SAME: "-target-feature" "+za128rs"
+// MCPU-RVA20S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-RVA20S64-SAME: "-target-feature" "+sstvala"
+// MCPU-RVA20S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-RVA20S64-SAME: "-target-feature" "+svade"
+// MCPU-RVA20S64-SAME: "-target-feature" "+svbare"
+// MCPU-RVA20S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rva22u64 | FileCheck
-check-prefix=MCPU-RVA22U64 %s
+// MCPU-RVA22U64: "-target-cpu" "rva22u64"
+// MCPU-RVA22U64-SAME: "-target-feature" "+m"
+// MCPU-RVA22U64-SAME: "-target-feature" "+a"
+// MCPU-RVA22U64-SAME: "-target-feature" "+f"
+// MCPU-RVA22U64-SAME: "-target-feature" "+d"
+// MCPU-RVA22U64-SAME: "-target-feature" "+c"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zic64b"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zicbom"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zicbop"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zicboz"
+// MCPU-RVA22U64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-RVA22U64-SAME: "-target-feature" "+ziccif"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zicclsm"
+// MCPU-RVA22U64-SAME: "-target-feature" "+ziccrse"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zicntr"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zicsr"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zihintpause"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zihpm"
+// MCPU-RVA22U64-SAME: "-target-feature" "+za64rs"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zfhmin"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zba"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zbb"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zbs"
+// MCPU-RVA22U64-SAME: "-target-feature" "+zkt"
+// MCPU-RVA22U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rva22s64 | FileCheck
-check-prefix=MCPU-RVA22S64 %s
+// MCPU-RVA22S64: "-target-cpu" "rva22s64"
+// MCPU-RVA22S64-SAME: "-target-feature" "+m"
+// MCPU-RVA22S64-SAME: "-target-feature" "+a"
+// MCPU-RVA22S64-SAME: "-target-feature" "+f"
+// MCPU-RVA22S64-SAME: "-target-feature" "+d"
+// MCPU-RVA22S64-SAME: "-target-feature" "+c"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zic64b"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zicbom"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zicbop"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zicboz"
+// MCPU-RVA22S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-RVA22S64-SAME: "-target-feature" "+ziccif"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-RVA22S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zicntr"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zicsr"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zifencei"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zihintpause"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zihpm"
+// MCPU-RVA22S64-SAME: "-target-feature" "+za64rs"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zfhmin"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zba"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zbb"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zbs"
+// MCPU-RVA22S64-SAME: "-target-feature" "+zkt"
+// MCPU-RVA22S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-RVA22S64-SAME: "-target-feature" "+sscounterenw"
+// MCPU-RVA22S64-SAME: "-target-feature" "+sstvala"
+// MCPU-RVA22S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-RVA22S64-SAME: "-target-feature" "+svade"
+// MCPU-RVA22S64-SAME: "-target-feature" "+svbare"
+// MCPU-RVA22S64-SAME: "-target-feature" "+svinval"
+// MCPU-RVA22S64-SAME: "-target-feature" "+svpbmt"
+// MCPU-RVA22S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rva23u64
-menable-experimental-extensions \
+// RUN: | FileCheck -check-prefix=MCPU-RVA23U64 %s
+// MCPU-RVA23U64: "-target-cpu" "rva23u64"
+// MCPU-RVA23U64-SAME: "-target-feature" "+m"
+// MCPU-RVA23U64-SAME: "-target-feature" "+a"
+// MCPU-RVA23U64-SAME: "-target-feature" "+f"
+// MCPU-RVA23U64-SAME: "-target-feature" "+d"
+// MCPU-RVA23U64-SAME: "-target-feature" "+c"
+// MCPU-RVA23U64-SAME: "-target-feature" "+v"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zic64b"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zicbom"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zicbop"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zicboz"
+// MCPU-RVA23U64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-RVA23U64-SAME: "-target-feature" "+ziccif"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zicclsm"
+// MCPU-RVA23U64-SAME: "-target-feature" "+ziccrse"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zicntr"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zicond"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zicsr"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zihintntl"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zihintpause"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zihpm"
+// MCPU-RVA23U64-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-RVA23U64-SAME: "-target-feature" "+za64rs"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zawrs"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zfa"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zfhmin"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zcb"
+// MCPU-RVA23U64-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zba"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zbb"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zbs"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zkt"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zvbb"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zvfhmin"
+// MCPU-RVA23U64-SAME: "-target-feature" "+zvkt"
+// MCPU-RVA23U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rva23s64
-menable-experimental-extensions \
+// RUN: | FileCheck -check-prefix=MCPU-RVA23S64 %s
+// MCPU-RVA23S64: "-target-cpu" "rva23s64"
+// MCPU-RVA23S64-SAME: "-target-feature" "+m"
+// MCPU-RVA23S64-SAME: "-target-feature" "+a"
+// MCPU-RVA23S64-SAME: "-target-feature" "+f"
+// MCPU-RVA23S64-SAME: "-target-feature" "+d"
+// MCPU-RVA23S64-SAME: "-target-feature" "+c"
+// MCPU-RVA23S64-SAME: "-target-feature" "+v"
+// MCPU-RVA23S64-SAME: "-target-feature" "+h"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zic64b"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zicbom"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zicbop"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zicboz"
+// MCPU-RVA23S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-RVA23S64-SAME: "-target-feature" "+ziccif"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-RVA23S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zicntr"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zicond"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zicsr"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zifencei"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zihintntl"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zihintpause"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zihpm"
+// MCPU-RVA23S64-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-RVA23S64-SAME: "-target-feature" "+za64rs"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zawrs"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zfa"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zfhmin"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zcb"
+// MCPU-RVA23S64-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zba"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zbb"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zbs"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zkt"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zvbb"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zvfhmin"
+// MCPU-RVA23S64-SAME: "-target-feature" "+zvkt"
+// MCPU-RVA23S64-SAME: "-target-feature" "+shcounterenw"
+// MCPU-RVA23S64-SAME: "-target-feature" "+shgatpa"
+// MCPU-RVA23S64-SAME: "-target-feature" "+shtvala"
+// MCPU-RVA23S64-SAME: "-target-feature" "+shvsatpa"
+// MCPU-RVA23S64-SAME: "-target-feature" "+shvstvala"
+// MCPU-RVA23S64-SAME: "-target-feature" "+shvstvecd"
+// MCPU-RVA23S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-RVA23S64-SAME: "-target-feature" "+sscofpmf"
+// MCPU-RVA23S64-SAME: "-target-feature" "+sscounterenw"
+// MCPU-RVA23S64-SAME: "-target-feature" "+experimental-ssnpm"
+// MCPU-RVA23S64-SAME: "-target-feature" "+ssstateen"
+// MCPU-RVA23S64-SAME: "-target-feature" "+sstc"
+// MCPU-RVA23S64-SAME: "-target-feature" "+sstvala"
+// MCPU-RVA23S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-RVA23S64-SAME: "-target-feature" "+ssu64xl"
+// MCPU-RVA23S64-SAME: "-target-feature" "+svade"
+// MCPU-RVA23S64-SAME: "-target-feature" "+svbare"
+// MCPU-RVA23S64-SAME: "-target-feature" "+svinval"
+// MCPU-RVA23S64-SAME: "-target-feature" "+svnapot"
+// MCPU-RVA23S64-SAME: "-target-feature" "+svpbmt"
+// MCPU-RVA23S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rvb23u64
-menable-experimental-extensions \
+// RUN: | FileCheck -check-prefix=MCPU-RVB23U64 %s
+// MCPU-RVB23U64: "-target-cpu" "rvb23u64"
+// MCPU-RVB23U64-SAME: "-target-feature" "+m"
+// MCPU-RVB23U64-SAME: "-target-feature" "+a"
+// MCPU-RVB23U64-SAME: "-target-feature" "+f"
+// MCPU-RVB23U64-SAME: "-target-feature" "+d"
+// MCPU-RVB23U64-SAME: "-target-feature" "+c"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zic64b"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zicbom"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zicbop"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zicboz"
+// MCPU-RVB23U64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-RVB23U64-SAME: "-target-feature" "+ziccif"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zicclsm"
+// MCPU-RVB23U64-SAME: "-target-feature" "+ziccrse"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zicntr"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zicond"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zicsr"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zihintntl"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zihintpause"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zihpm"
+// MCPU-RVB23U64-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-RVB23U64-SAME: "-target-feature" "+za64rs"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zawrs"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zfa"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zcb"
+// MCPU-RVB23U64-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zba"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zbb"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zbs"
+// MCPU-RVB23U64-SAME: "-target-feature" "+zkt"
+// MCPU-RVB23U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rvb23s64
-menable-experimental-extensions \
+// RUN: | FileCheck -check-prefix=MCPU-RVB23S64 %s
+// MCPU-RVB23S64: "-target-cpu" "rvb23s64"
+// MCPU-RVB23S64-SAME: "-target-feature" "+m"
+// MCPU-RVB23S64-SAME: "-target-feature" "+a"
+// MCPU-RVB23S64-SAME: "-target-feature" "+f"
+// MCPU-RVB23S64-SAME: "-target-feature" "+d"
+// MCPU-RVB23S64-SAME: "-target-feature" "+c"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zic64b"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zicbom"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zicbop"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zicboz"
+// MCPU-RVB23S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-RVB23S64-SAME: "-target-feature" "+ziccif"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-RVB23S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zicntr"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zicond"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zicsr"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zifencei"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zihintntl"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zihintpause"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zihpm"
+// MCPU-RVB23S64-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-RVB23S64-SAME: "-target-feature" "+za64rs"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zawrs"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zfa"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zcb"
+// MCPU-RVB23S64-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zba"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zbb"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zbs"
+// MCPU-RVB23S64-SAME: "-target-feature" "+zkt"
+// MCPU-RVB23S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-RVB23S64-SAME: "-target-feature" "+sscofpmf"
+// MCPU-RVB23S64-SAME: "-target-feature" "+sscounterenw"
+// MCPU-RVB23S64-SAME: "-target-feature" "+sstc"
+// MCPU-RVB23S64-SAME: "-target-feature" "+sstvala"
+// MCPU-RVB23S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-RVB23S64-SAME: "-target-feature" "+ssu64xl"
+// MCPU-RVB23S64-SAME: "-target-feature" "+svade"
+// MCPU-RVB23S64-SAME: "-target-feature" "+svbare"
+// MCPU-RVB23S64-SAME: "-target-feature" "+svinval"
+// MCPU-RVB23S64-SAME: "-target-feature" "+svnapot"
+// MCPU-RVB23S64-SAME: "-target-feature" "+svpbmt"
+// MCPU-RVB23S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rvm23u32
-menable-experimental-extensions \
+// RUN: | FileCheck -check-prefix=MCPU-RVM23U32 %s
+// MCPU-RVM23U32: "-target-cpu" "rvm23u32"
+// MCPU-RVM23U32-SAME: "-target-feature" "+m"
+// MCPU-RVM23U32-SAME: "-target-feature" "+zicbop"
+// MCPU-RVM23U32-SAME: "-target-feature" "+zicond"
+// MCPU-RVM23U32-SAME: "-target-feature" "+zicsr"
+// MCPU-RVM23U32-SAME: "-target-feature" "+zihintntl"
+// MCPU-RVM23U32-SAME: "-target-feature" "+zihintpause"
+// MCPU-RVM23U32-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-RVM23U32-SAME: "-target-feature" "+zce"
+// MCPU-RVM23U32-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-RVM23U32-SAME: "-target-feature" "+zba"
+// MCPU-RVM23U32-SAME: "-target-feature" "+zbb"
+// MCPU-RVM23U32-SAME: "-target-feature" "+zbs"
+// MCPU-RVM23U32-SAME: "-target-abi" "ilp32"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 41347f9ed7aa14..6270a887e89280 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -81,16 +81,16 @@
// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV32
// RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32,
generic-rvi20u32, generic-rvm23u32, rocket-rv32, sifive-e20, sifive-e21,
sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base,
syntacore-scr1-max{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rvi20u32,
rvm23u32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31,
sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}}
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
generic-rva20s64, generic-rva20u64, generic-rva22s64, generic-rva22u64,
generic-rva23s64, generic-rva23u64, generic-rvb23s64, generic-rvb23u64,
generic-rvi20u64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21,
sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280,
veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rva20s64,
rva20u64, rva22s64, rva22u64, rva23s64, rva23u64, rvb23s64, rvb23u64, rvi20u64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32,
generic-rvi20u32, generic-rvm23u32, rocket-rv32, sifive-e20, sifive-e21,
sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base,
syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32,
rvi20u32, rvm23u32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24,
sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max,
generic, rocket, sifive-7-series{{$}}
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
generic-rva20s64, generic-rva20u64, generic-rva22s64, generic-rva22u64,
generic-rva23s64, generic-rva23u64, generic-rvb23s64, generic-rvb23u64,
generic-rvi20u64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21,
sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280,
veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rva20s64, rva20u64, rva22s64, rva22u64, rva23s64, rva23u64, rvb23s64, rvb23u64,
rvi20u64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51,
sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1,
xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 9c0ca06de0a5a8..135cdf63de3c04 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -237,37 +237,37 @@ def GENERIC_RV32 :
RISCVGenericProcessorModel<"generic-rv32",
def GENERIC_RV64 : RISCVGenericProcessorModel<"generic-rv64",
[Feature64Bit]>;
-def GENERIC_RVI20U32 : RISCVGenericProcessorModel<"generic-rvi20u32",
+def GENERIC_RVI20U32 : RISCVGenericProcessorModel<"rvi20u32",
[Feature32Bit]>;
-def GENERIC_RVI20U64 : RISCVGenericProcessorModel<"generic-rvi20u64",
+def GENERIC_RVI20U64 : RISCVGenericProcessorModel<"rvi20u64",
[Feature64Bit]>;
-def GENERIC_RVA20U64 : RISCVGenericProcessorModel<"generic-rva20u64",
+def GENERIC_RVA20U64 : RISCVGenericProcessorModel<"rva20u64",
RVA20U64Features>;
-def GENERIC_RVA20S64 : RISCVGenericProcessorModel<"generic-rva20s64",
+def GENERIC_RVA20S64 : RISCVGenericProcessorModel<"rva20s64",
RVA20S64Features>;
-def GENERIC_RVA22U64 : RISCVGenericProcessorModel<"generic-rva22u64",
+def GENERIC_RVA22U64 : RISCVGenericProcessorModel<"rva22u64",
RVA22U64Features>;
-def GENERIC_RVA22S64 : RISCVGenericProcessorModel<"generic-rva22s64",
+def GENERIC_RVA22S64 : RISCVGenericProcessorModel<"rva22s64",
RVA22S64Features>;
-def GENERIC_RVA23U64 : RISCVGenericProcessorModel<"generic-rva23u64",
+def GENERIC_RVA23U64 : RISCVGenericProcessorModel<"rva23u64",
RVA23U64Features>;
-def GENERIC_RVA23S64 : RISCVGenericProcessorModel<"generic-rva23s64",
+def GENERIC_RVA23S64 : RISCVGenericProcessorModel<"rva23s64",
RVA23S64Features>;
-def GENERIC_RVB23U64 : RISCVGenericProcessorModel<"generic-rvb23u64",
+def GENERIC_RVB23U64 : RISCVGenericProcessorModel<"rvb23u64",
RVB23U64Features>;
-def GENERIC_RVB23S64 : RISCVGenericProcessorModel<"generic-rvb23s64",
+def GENERIC_RVB23S64 : RISCVGenericProcessorModel<"rvb23s64",
RVB23S64Features>;
-def GENERIC_RVM23U32 : RISCVGenericProcessorModel<"generic-rvm23u32",
+def GENERIC_RVM23U32 : RISCVGenericProcessorModel<"rvm23u32",
RVM23U32Features>;
// Support generic for compatibility with other targets. The triple will be
used
>From e03f2cdcc4d9ebdc6f462495c34772f5debb2cc3 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng...@bytedance.com>
Date: Fri, 26 Apr 2024 15:59:55 +0800
Subject: [PATCH 3/7] We should add FeatureStdExtI explicitly now
Created using spr 1.3.6-beta.1
---
llvm/lib/Target/RISCV/RISCVProfiles.td | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td
b/llvm/lib/Target/RISCV/RISCVProfiles.td
index 1ba76264172e62..7881c9157a46ff 100644
--- a/llvm/lib/Target/RISCV/RISCVProfiles.td
+++ b/llvm/lib/Target/RISCV/RISCVProfiles.td
@@ -10,6 +10,9 @@ class RISCVProfile<string name, list<SubtargetFeature>
features>
: SubtargetFeature<name, "RISCVProfile", NAME,
"RISC-V " # name # " profile", features>;
+defvar RVI20U32Features = [Feature32Bit, FeatureStdExtI];
+defvar RVI20U64Features = [Feature64Bit, FeatureStdExtI];
+
defvar RVA20U64Features = [Feature64Bit,
FeatureStdExtI,
FeatureStdExtM,
@@ -188,8 +191,8 @@ defvar RVM23U32Features = [Feature32Bit,
FeatureStdExtZimop,
FeatureStdExtZcmop];
-def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit]>;
-def RVI20U64 : RISCVProfile<"rvi20u64", [Feature64Bit]>;
+def RVI20U32 : RISCVProfile<"rvi20u32", RVI20U32Features>;
+def RVI20U64 : RISCVProfile<"rvi20u64", RVI20U64Features>;
def RVA20U64 : RISCVProfile<"rva20u64", RVA20U64Features>;
def RVA20S64 : RISCVProfile<"rva20s64", RVA20S64Features>;
def RVA22U64 : RISCVProfile<"rva22u64", RVA22U64Features>;
>From c5f08b61d9256807e3ac69828afe4cb07d3284e2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng...@bytedance.com>
Date: Fri, 26 Apr 2024 17:27:05 +0800
Subject: [PATCH 4/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?=
=?UTF-8?q?anges=20introduced=20through=20rebase?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6-beta.1
[skip ci]
---
llvm/test/TableGen/riscv-target-def.td | 6 ++++--
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/llvm/test/TableGen/riscv-target-def.td
b/llvm/test/TableGen/riscv-target-def.td
index b23c7e4d40198b..175b68f9f8bad7 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -83,6 +83,7 @@ def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
FeatureStdExtI,
FeatureStdExtZifencei,
FeatureStdExtZicsr,
+ FeatureStdExtZidummy,
FeatureDummy]>;
def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
NoSchedModel,
@@ -90,6 +91,7 @@ def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
FeatureStdExtI,
FeatureStdExtZifencei,
FeatureStdExtZicsr,
+ FeatureStdExtZidummy,
FeatureDummy]>;
def ROCKET : RISCVTuneProcessorModel<"rocket",
NoSchedModel>;
@@ -127,8 +129,8 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0)
// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0)
-// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"},
{"rv32i2p1_zicsr2p0_zifencei2p0"}, 0)
-// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"},
{"rv64i2p1_zicsr2p0_zifencei2p0"}, 0)
+// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"},
{"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0)
+// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"},
{"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0)
// CHECK: #undef PROC
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 217b531dcfd394..4580a0ab12669c 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -119,7 +119,7 @@ static void printMArch(raw_ostream &OS, const Record &Rec) {
// Convert features to FeatureVector.
for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
- StringRef FeatureName = Feature->getValueAsString("Name");
+ StringRef FeatureName = getExtensionName(Feature);
if (Feature->isSubClassOf("RISCVExtension")) {
unsigned Major = Feature->getValueAsInt("MajorVersion");
unsigned Minor = Feature->getValueAsInt("MinorVersion");
>From cf6a0233f40424db8c0fbdb304305b08caaf082c Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng...@bytedance.com>
Date: Fri, 26 Apr 2024 18:41:49 +0800
Subject: [PATCH 5/7] Remove getRISCVProfile()
Created using spr 1.3.6-beta.1
---
llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h
b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 191a6e5aec9854..28a639ef7a7d03 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -155,8 +155,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
/// initializeProperties().
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
- RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
-
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
bool GETTER() const { return ATTRIBUTE; }
#include "RISCVGenSubtargetInfo.inc"
>From f51cf9a46902e4bc4d00ed8f45a99dee321963f2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng...@bytedance.com>
Date: Fri, 26 Apr 2024 23:29:50 +0800
Subject: [PATCH 6/7] Remove RISCVProfileEnum
Created using spr 1.3.6-beta.1
---
llvm/lib/Target/RISCV/RISCVProfiles.td | 2 +-
llvm/lib/Target/RISCV/RISCVSubtarget.h | 17 -----------------
2 files changed, 1 insertion(+), 18 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td
b/llvm/lib/Target/RISCV/RISCVProfiles.td
index 7881c9157a46ff..5c13710faf65b9 100644
--- a/llvm/lib/Target/RISCV/RISCVProfiles.td
+++ b/llvm/lib/Target/RISCV/RISCVProfiles.td
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
class RISCVProfile<string name, list<SubtargetFeature> features>
- : SubtargetFeature<name, "RISCVProfile", NAME,
+ : SubtargetFeature<name, "Is" # NAME, "true",
"RISC-V " # name # " profile", features>;
defvar RVI20U32Features = [Feature32Bit, FeatureStdExtI];
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h
b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 28a639ef7a7d03..85f8f5f654fe7c 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -65,27 +65,10 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
VentanaVeyron,
};
// clang-format on
-
- enum RISCVProfileEnum : uint8_t {
- Unspecified,
- RVI20U32,
- RVI20U64,
- RVA20U64,
- RVA20S64,
- RVA22U64,
- RVA22S64,
- RVA23U64,
- RVA23S64,
- RVB23U64,
- RVB23S64,
- RVM23U32,
- };
-
private:
virtual void anchor();
RISCVProcFamilyEnum RISCVProcFamily = Others;
- RISCVProfileEnum RISCVProfile = Unspecified;
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
bool ATTRIBUTE = DEFAULT;
>From cf5591b38ab29077bc070cade25c650ad9a1d1bd Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng...@bytedance.com>
Date: Sat, 27 Apr 2024 00:36:48 +0800
Subject: [PATCH 7/7] Move RISCVProfiles.td next to RISCVFeatures.td
Created using spr 1.3.6-beta.1
---
llvm/lib/Target/RISCV/RISCV.td | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index e6536841b205a8..09f496574d64ae 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -14,6 +14,12 @@ include "llvm/Target/Target.td"
include "RISCVFeatures.td"
+//===----------------------------------------------------------------------===//
+// RISC-V profiles supported.
+//===----------------------------------------------------------------------===//
+
+include "RISCVProfiles.td"
+
//===----------------------------------------------------------------------===//
// Named operands for CSR instructions.
//===----------------------------------------------------------------------===//
@@ -47,12 +53,6 @@ include "RISCVSchedSiFiveP600.td"
include "RISCVSchedSyntacoreSCR1.td"
include "RISCVSchedXiangShanNanHu.td"
-//===----------------------------------------------------------------------===//
-// RISC-V profiles supported.
-//===----------------------------------------------------------------------===//
-
-include "RISCVProfiles.td"
-
//===----------------------------------------------------------------------===//
// RISC-V processors supported.
//===----------------------------------------------------------------------===//
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