llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Pengcheng Wang (wangpc-pp) <details> <summary>Changes</summary> This PR includes: * vsadd.vv/vsaddu.vv * vaadd.vv/vaaddu.vv * vsmul.vv --- Full diff: https://github.com/llvm/llvm-project/pull/90372.diff 3 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+5) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+16-13) - (modified) llvm/test/CodeGen/RISCV/rvv/commutable.ll (+6-8) ``````````diff diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 3efd09aeae879d..8cb9a40a98bcd8 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3132,6 +3132,11 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI, case CASE_RVV_OPCODE_WIDEN(VWMACC_VV): case CASE_RVV_OPCODE_WIDEN(VWMACCU_VV): case CASE_RVV_OPCODE_UNMASK(VADC_VVM): + case CASE_RVV_OPCODE(VSADD_VV): + case CASE_RVV_OPCODE(VSADDU_VV): + case CASE_RVV_OPCODE(VAADD_VV): + case CASE_RVV_OPCODE(VAADDU_VV): + case CASE_RVV_OPCODE(VSMUL_VV): // Operands 2 and 3 are commutable. return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3); case CASE_VFMA_SPLATS(FMADD): diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index e9715b40adc079..fc60a9cc7cd30e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -2146,8 +2146,9 @@ multiclass VPseudoBinaryRoundingMode<VReg RetClass, string Constraint = "", int sew = 0, int UsesVXRM = 1, - int TargetConstraintType = 1> { - let VLMul = MInfo.value, SEW=sew in { + int TargetConstraintType = 1, + bit Commutable = 0> { + let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in { defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); def suffix : VPseudoBinaryNoMaskRoundingMode<RetClass, Op1Class, Op2Class, Constraint, UsesVXRM, @@ -2232,8 +2233,9 @@ multiclass VPseudoBinaryV_VV<LMULInfo m, string Constraint = "", int sew = 0, bi defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew, Commutable=Commutable>; } -multiclass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = ""> { - defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m, Constraint>; +multiclass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = "", bit Commutable = 0> { + defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m, Constraint, + Commutable=Commutable>; } // Similar to VPseudoBinaryV_VV, but uses MxListF. @@ -2715,10 +2717,11 @@ multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> } } -multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> { +multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = "", + bit Commutable = 0> { foreach m = MxList in { defvar mx = m.MX; - defm "" : VPseudoBinaryV_VV<m, Constraint>, + defm "" : VPseudoBinaryV_VV<m, Constraint, Commutable=Commutable>, SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUX", mx, forceMergeOpRead=true>; defm "" : VPseudoBinaryV_VX<m, Constraint>, @@ -2788,7 +2791,7 @@ multiclass VPseudoVSALU_VV_VX { multiclass VPseudoVSMUL_VV_VX_RM { foreach m = MxList in { defvar mx = m.MX; - defm "" : VPseudoBinaryV_VV_RM<m>, + defm "" : VPseudoBinaryV_VV_RM<m, Commutable=1>, SchedBinary<"WriteVSMulV", "ReadVSMulV", "ReadVSMulV", mx, forceMergeOpRead=true>; defm "" : VPseudoBinaryV_VX_RM<m>, @@ -2797,10 +2800,10 @@ multiclass VPseudoVSMUL_VV_VX_RM { } } -multiclass VPseudoVAALU_VV_VX_RM { +multiclass VPseudoVAALU_VV_VX_RM<bit Commutable = 0> { foreach m = MxList in { defvar mx = m.MX; - defm "" : VPseudoBinaryV_VV_RM<m>, + defm "" : VPseudoBinaryV_VV_RM<m, Commutable=Commutable>, SchedBinary<"WriteVAALUV", "ReadVAALUV", "ReadVAALUV", mx, forceMergeOpRead=true>; defm "" : VPseudoBinaryV_VX_RM<m>, @@ -6448,8 +6451,8 @@ defm PseudoVMV_V : VPseudoUnaryVMV_V_X_I; // 12.1. Vector Single-Width Saturating Add and Subtract //===----------------------------------------------------------------------===// let Defs = [VXSAT], hasSideEffects = 1 in { - defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI; - defm PseudoVSADD : VPseudoVSALU_VV_VX_VI; + defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI<Commutable=1>; + defm PseudoVSADD : VPseudoVSALU_VV_VX_VI<Commutable=1>; defm PseudoVSSUBU : VPseudoVSALU_VV_VX; defm PseudoVSSUB : VPseudoVSALU_VV_VX; } @@ -6457,8 +6460,8 @@ let Defs = [VXSAT], hasSideEffects = 1 in { //===----------------------------------------------------------------------===// // 12.2. Vector Single-Width Averaging Add and Subtract //===----------------------------------------------------------------------===// -defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM; -defm PseudoVAADD : VPseudoVAALU_VV_VX_RM; +defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM<Commutable=1>; +defm PseudoVAADD : VPseudoVAALU_VV_VX_RM<Commutable=1>; defm PseudoVASUBU : VPseudoVAALU_VV_VX_RM; defm PseudoVASUB : VPseudoVAALU_VV_VX_RM; diff --git a/llvm/test/CodeGen/RISCV/rvv/commutable.ll b/llvm/test/CodeGen/RISCV/rvv/commutable.ll index e383c1b477c45d..06a6327d3892b6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/commutable.ll +++ b/llvm/test/CodeGen/RISCV/rvv/commutable.ll @@ -724,10 +724,9 @@ define <vscale x 1 x i64> @commutable_vaadd_vv(<vscale x 1 x i64> %0, <vscale x ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 -; CHECK-NEXT: vaadd.vv v10, v8, v9 -; CHECK-NEXT: vaadd.vv v8, v9, v8 +; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma -; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen 0, iXLen %2) @@ -743,7 +742,7 @@ define <vscale x 1 x i64> @commutable_vaadd_vv_masked(<vscale x 1 x i64> %0, <vs ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vaadd.vv v10, v8, v9, v0.t -; CHECK-NEXT: vaadd.vv v8, v9, v8, v0.t +; CHECK-NEXT: vaadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret @@ -760,10 +759,9 @@ define <vscale x 1 x i64> @commutable_vaaddu_vv(<vscale x 1 x i64> %0, <vscale x ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 -; CHECK-NEXT: vaaddu.vv v10, v8, v9 -; CHECK-NEXT: vaaddu.vv v8, v9, v8 +; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma -; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen 0, iXLen %2) @@ -779,7 +777,7 @@ define <vscale x 1 x i64> @commutable_vaaddu_vv_masked(<vscale x 1 x i64> %0, <v ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vaaddu.vv v10, v8, v9, v0.t -; CHECK-NEXT: vaaddu.vv v8, v9, v8, v0.t +; CHECK-NEXT: vaaddu.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret `````````` </details> https://github.com/llvm/llvm-project/pull/90372 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
