Guillaume Gastebois schrieb: > Hello, > > I modified these registers. But the scanner locks writting continiously : > "[genesys] sanei_genesys_read_register (0x41, 0xf4) completed". > > I modified 0x1a=0x24 and 0x1d=0x02 in Genesys_Sensor. In log I see > 0x1d=0x02 but 0x1a=0x00 ??
For the missing change of 0x1a: The code block for setting this value (along with 0x1b..0x1d, which is then hardcoded to 0x02) is commented out, genesys_gl841.c:1159. This is probably the case, because they were not needed for my specific scanner. I cannot explain the lockup. I'd play around with different sets of registers and see if they work. But i guess, register 0x1a is a key to get the rest working. > I will be long for next answer as I take one week holidays ! I hope you had a nice week holidays. Regards, Pierre > regards > Guillaume > > Pierre Willenbrock a ?crit : >> Hi, >> >> Guillaume Gastebois schrieb: >>> Hello, >>> >>>> So, we need to check what parts of the clocking we need to setup >>>> differently. >>>> >>>> Candidates: >>>> >>>> reg sane windows >>>> 0x1a 0x00 0x24 enable clock 3,4 manual output, invert clock 4 >>>> 0x1d 0x04 0x02 just a smaller toggle "shoulder". >>>> 0x71 0x00 0x05 RS signal seems to be not used. >>>> 0x72 0x00 0x07 CP signal seems to be not used. >>>> 0x73 0x00 0x09 CP signal seems to be not used. >>>> 0x75 0x00 0x01 clock 1 bitmap >>>> 0x76 0x00 0xff clock 1 bitmap >>>> 0x79 0x00 0x3f clock 3 bitmap >>>> 0x7c 0x00 0x1e clock 4 bitmap >>>> 0x7d 0x00 0x11 change RS on falling edge of system clock, use DLY >>>> 0x7f 0x00 0x50 delay each of BSMP and VSMP by 8.33ns (DLY) >>>> >>>> The clock 1 stuff seems to be not needed, as it is in automatic mode. >>>> But clock 3/4 look interesting. The delay of BSMP/VSMP may be useful, too. >>>> >>> 0x1a was still 0x24. I modified 0x1d which was 0x04 to 0x02. Result is >>> on http://ggastebois.free.fr/lide90_snoop/22_test1.tar. >>> >>> I doesn't find where to modify 0x71-0x7f !!! >> Add them to gl841_init_registers. >> >>>>> Another thing : I always have a brither vertical line where there is a >>>>> small black rectangle in the calibration area. >>>> The small black rectangle is included when acquiring the white level. >>>> Reduce shading_lines(second to last entry) in Genesys_Model to 250, that >>>> way it is not seen anymore. >>>> >>> Done, works. >>> >>>> Oh, and please update from cvs again. A small mistake in >>>> gl841_bulk_write_registers made the debug register dumps useless. >>>> >>> Done. >>> >>> >>> Another thing : when I make several scan with sane backend and sane >>> command line, I have alternatively brite and dark images !!! Why ??? >> The calibration is probably giving widely differing results with >> different starting conditions. It swings between two states. But you >> shouldn't see this after the gl842 did its shading correction. Then, the >> problem is probably overexposure of the ccd cells. Try reducing the >> upper threshold in genesys_gl841.c:4383 >> >> if (avge > 2000) { >> expr = (expr * 2000) / avge; >> expg = (expg * 2000) / avge; >> expb = (expb * 2000) / avge; >> >> Reducing the lower threshold may be needed, too. The current values for >> your scanner are: >> expr: 1235 >> expg: 1235 >> expb: 675 >> >> No guarantee that this helps at all. >> >>> Regards >>> Guillaume >> Further, we need to figure out a way to get the LEDs go completely dark. >> 0x101 is just about half of 675. I will experiment a bit with my >> scanner, to find out if the gl842 can do that. >> >> Regards, >> Pierre >> >> >