[clang] [llvm] [mlir] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
@@ -23,8 +26,8 @@ struct B : A {
void g(A *a) { a->foo(); }
// CHECK1-LABEL: define{{.*}} void @_ZN5test14fooAEv()
-// CHECK1: call void @_ZN5test11AC1Ev(ptr
-// CHECK1: %[[VTABLE:.*]] = load ptr addrspace(1), ptr %{{.*}}
+// CHECK1: call{{.*}} void @_ZN5test11AC1Ev(ptr {{((addrspace(4)){0,1})}}
AlexVlx wrote:
Right, so what I'll do is: merge this as is, and then revisit the test and
rework it along the lines you and @jrtc27 are suggesting, since it looks as if
I'll need to mess with it again for another piece of work.
https://github.com/llvm/llvm-project/pull/88182
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[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
@@ -6088,6 +6088,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
StringRef Prefix =
llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch());
if (!Prefix.empty()) {
+if (Prefix == "spv" &&
+getTarget().getTriple().getOS() == llvm::Triple::OSType::AMDHSA)
+ Prefix = "amdgcn";
AlexVlx wrote:
I've fixed the `"spv"` exclusion. Circling back to the idea of moving the
prefix into `TargetInfo`, that seems like a pretty nice improvement - I think
we could also deal with scenarios like the one here where there's an union of
target specific builtins (spv & amdgcn in this case) by having some sort of
parent-child / main-aux relationship. It should probably be a separate PR since
it's an independent piece of functionality (and I've not thought through it
fully yet) - unless you disagree?
https://github.com/llvm/llvm-project/pull/89796
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[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
@@ -6088,6 +6088,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
StringRef Prefix =
llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch());
if (!Prefix.empty()) {
+if (Prefix == "spv" &&
+getTarget().getTriple().getOS() == llvm::Triple::OSType::AMDHSA)
+ Prefix = "amdgcn";
AlexVlx wrote:
The second bit is actually a good catch, I had assumed there's no SPIRV
builtins, however looking at it it seems a few exist, so it appears we'll need
both. I'll rework this part, cheers!
https://github.com/llvm/llvm-project/pull/89796
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[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx commented: > @AlexVlx, do you think it's worth promoting > [SPV_INTEL_inline_assembly](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_inline_assembly.asciidoc) > and > [SPV_INTEL_function_pointers](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_function_pointers.asciidoc) > to Khronos extensions? I would definitely say so, although I expect the ASM one to be controversial. https://github.com/llvm/llvm-project/pull/89796 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/89796 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx commented: > Please fix the commit message before you merge; otherwise LGTM For the commit message I was thinking something along the following lines: `At the moment, Clang is rather liberal in assuming that 0 (and by extension unqualified) is always a safe default. This does not work for targets that actually use a different value for the default / generic AS (for example, the SPIRV that obtains from HIPSPV or SYCL). This patch is a first, fairly safe step towards trying to clear things up by querying a modules default AS from the target, rather than assuming it's 0, alongside fixing a few places where things break / we encode the 0 AS assumption. A bunch of existing tests are extended to check for non-zero default AS usage.` https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/7] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/Basic/Targets.cpp | 6 +-
clang/lib/Basic/Targets/SPIR.cpp | 288 +
clang/lib/Basic/Targets/SPIR.h| 51 +++
clang/lib/CodeGen/CGBuiltin.cpp | 7 +
clang/test/CodeGen/target-data.c | 4 +
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++
...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++
clang/test/CodeGenCUDA/long-double.cu | 4 +
clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129
.../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++
clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++
.../spirv-amdgcn-dpp-const-fold.hip | 46 +++
clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 +
.../predefined-macros-no-warnings.c | 1 +
clang/test/Preprocessor/predefined-macros.c | 10 +
...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++
.../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++
clang/test/SemaCUDA/allow-int128.cu | 3 +
clang/test/SemaCUDA/amdgpu-f128.cu| 1 +
clang/test/SemaCUDA/float16.cu| 1 +
clang/test/SemaCUDA/fp16-arg-return.cu| 1 +
.../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +
22 files changed, 1178 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
create mode 100644
clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip
create mode 100644
clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3283510c6aac..04a13e3385d1f 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const
llvm::Triple ,
}
case llvm::Triple::spirv64: {
if (os != llvm::Triple::UnknownOS ||
-Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
+ if (os == llvm::Triple::OSType::AMDHSA)
+return std::make_unique(Triple, Opts);
+
return nullptr;
+}
return std::make_unique(Triple, Opts);
}
case llvm::Triple::wasm32:
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index dc920177d3a91..d7d232ac9484f 100644
--- a/clang/lib/Basic/Targets/SPIR.cpp
+++ b/clang/lib/Basic/Targets/SPIR.cpp
@@ -12,6 +12,8 @@
#include "SPIR.h"
#include "Targets.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
using namespace clang;
using namespace clang::targets;
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
\
+ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)
\
+ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#include "clang/Basic/BuiltinsAMDGPU.def"
+};
+
+namespace {
+const char *AMDGPUGCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+
[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/7] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/Basic/Targets.cpp | 6 +-
clang/lib/Basic/Targets/SPIR.cpp | 288 +
clang/lib/Basic/Targets/SPIR.h| 51 +++
clang/lib/CodeGen/CGBuiltin.cpp | 7 +
clang/test/CodeGen/target-data.c | 4 +
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++
...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++
clang/test/CodeGenCUDA/long-double.cu | 4 +
clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129
.../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++
clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++
.../spirv-amdgcn-dpp-const-fold.hip | 46 +++
clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 +
.../predefined-macros-no-warnings.c | 1 +
clang/test/Preprocessor/predefined-macros.c | 10 +
...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++
.../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++
clang/test/SemaCUDA/allow-int128.cu | 3 +
clang/test/SemaCUDA/amdgpu-f128.cu| 1 +
clang/test/SemaCUDA/float16.cu| 1 +
clang/test/SemaCUDA/fp16-arg-return.cu| 1 +
.../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +
22 files changed, 1178 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
create mode 100644
clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip
create mode 100644
clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3283510c6aac..04a13e3385d1f 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const
llvm::Triple ,
}
case llvm::Triple::spirv64: {
if (os != llvm::Triple::UnknownOS ||
-Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
+ if (os == llvm::Triple::OSType::AMDHSA)
+return std::make_unique(Triple, Opts);
+
return nullptr;
+}
return std::make_unique(Triple, Opts);
}
case llvm::Triple::wasm32:
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index dc920177d3a91..d7d232ac9484f 100644
--- a/clang/lib/Basic/Targets/SPIR.cpp
+++ b/clang/lib/Basic/Targets/SPIR.cpp
@@ -12,6 +12,8 @@
#include "SPIR.h"
#include "Targets.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
using namespace clang;
using namespace clang::targets;
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
\
+ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)
\
+ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#include "clang/Basic/BuiltinsAMDGPU.def"
+};
+
+namespace {
+const char *AMDGPUGCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+
[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
@@ -0,0 +1,111 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -fsyntax-only -verify %s
+
+#pragma OPENCL EXTENSION cl_khr_fp64 : enable
+
+kernel void test () {
+
+ int sgpr = 0, vgpr = 0, imm = 0;
+
+ // sgpr constraints
+ __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "s" (imm) : );
+
+ __asm__ ("s_mov_b32 %0, %1" : "={s1}" (sgpr) : "{exec}" (imm) : );
+ __asm__ ("s_mov_b32 %0, %1" : "={s1}" (sgpr) : "{exe" (imm) : ); //
expected-error {{invalid input constraint '{exe' in asm}}
+ __asm__ ("s_mov_b32 %0, %1" : "={s1}" (sgpr) : "{exec" (imm) : ); //
expected-error {{invalid input constraint '{exec' in asm}}
+ __asm__ ("s_mov_b32 %0, %1" : "={s1}" (sgpr) : "{exec}a" (imm) : ); //
expected-error {{invalid input constraint '{exec}a' in asm}}
AlexVlx wrote:
We can use non-flavoured SPIRV for that, no? Once the rest of the toolchain
bits are in place, that'll work as well, and will offer neither ASM nor
builtins. Surely, if there's actual some groundswell of opposition to ASM,
folks will organically migrate. I'd say that's preferable to trying to force
users to do anything, which seldom works well.
https://github.com/llvm/llvm-project/pull/89796
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[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/7] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/Basic/Targets.cpp | 6 +-
clang/lib/Basic/Targets/SPIR.cpp | 288 +
clang/lib/Basic/Targets/SPIR.h| 51 +++
clang/lib/CodeGen/CGBuiltin.cpp | 7 +
clang/test/CodeGen/target-data.c | 4 +
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++
...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++
clang/test/CodeGenCUDA/long-double.cu | 4 +
clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129
.../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++
clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++
.../spirv-amdgcn-dpp-const-fold.hip | 46 +++
clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 +
.../predefined-macros-no-warnings.c | 1 +
clang/test/Preprocessor/predefined-macros.c | 10 +
...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++
.../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++
clang/test/SemaCUDA/allow-int128.cu | 3 +
clang/test/SemaCUDA/amdgpu-f128.cu| 1 +
clang/test/SemaCUDA/float16.cu| 1 +
clang/test/SemaCUDA/fp16-arg-return.cu| 1 +
.../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +
22 files changed, 1178 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
create mode 100644
clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip
create mode 100644
clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3283510c6aac..04a13e3385d1f 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const
llvm::Triple ,
}
case llvm::Triple::spirv64: {
if (os != llvm::Triple::UnknownOS ||
-Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
+ if (os == llvm::Triple::OSType::AMDHSA)
+return std::make_unique(Triple, Opts);
+
return nullptr;
+}
return std::make_unique(Triple, Opts);
}
case llvm::Triple::wasm32:
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index dc920177d3a91..d7d232ac9484f 100644
--- a/clang/lib/Basic/Targets/SPIR.cpp
+++ b/clang/lib/Basic/Targets/SPIR.cpp
@@ -12,6 +12,8 @@
#include "SPIR.h"
#include "Targets.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
using namespace clang;
using namespace clang::targets;
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
\
+ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)
\
+ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#include "clang/Basic/BuiltinsAMDGPU.def"
+};
+
+namespace {
+const char *AMDGPUGCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+
[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
@@ -0,0 +1,111 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -fsyntax-only -verify %s
+
+#pragma OPENCL EXTENSION cl_khr_fp64 : enable
+
+kernel void test () {
+
+ int sgpr = 0, vgpr = 0, imm = 0;
+
+ // sgpr constraints
+ __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "s" (imm) : );
+
+ __asm__ ("s_mov_b32 %0, %1" : "={s1}" (sgpr) : "{exec}" (imm) : );
+ __asm__ ("s_mov_b32 %0, %1" : "={s1}" (sgpr) : "{exe" (imm) : ); //
expected-error {{invalid input constraint '{exe' in asm}}
+ __asm__ ("s_mov_b32 %0, %1" : "={s1}" (sgpr) : "{exec" (imm) : ); //
expected-error {{invalid input constraint '{exec' in asm}}
+ __asm__ ("s_mov_b32 %0, %1" : "={s1}" (sgpr) : "{exec}a" (imm) : ); //
expected-error {{invalid input constraint '{exec}a' in asm}}
AlexVlx wrote:
I think that, whilst appealing, it'd be problematic in a few ways, but mainly
it'd relegate this to interesting tech experiment that is not particularly
useful to existing users. There's already oodles of AMDGCN ASM that has been
authored (a lot of it unguarded to boot); most of it is actually arithmetic,
that tickles numbered registers to achieve peak performance. Telling folks that
they need to rewrite swathes of their libs / core algorithms in order to get
SPIRV is highly likely to ensure they aggressively ignore it. To my mind this
is a necessary evil.
https://github.com/llvm/llvm-project/pull/89796
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[clang] [Clang][HIP] Warn when __AMDGCN_WAVEFRONT_SIZE is used in host code (PR #91478)
https://github.com/AlexVlx approved this pull request. This looks fine to me (I do hate that macro being defined on the host though, so I am biased). Thanks! https://github.com/llvm/llvm-project/pull/91478 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
@@ -23,8 +26,8 @@ struct B : A {
void g(A *a) { a->foo(); }
// CHECK1-LABEL: define{{.*}} void @_ZN5test14fooAEv()
-// CHECK1: call void @_ZN5test11AC1Ev(ptr
-// CHECK1: %[[VTABLE:.*]] = load ptr addrspace(1), ptr %{{.*}}
+// CHECK1: call{{.*}} void @_ZN5test11AC1Ev(ptr {{((addrspace(4)){0,1})}}
AlexVlx wrote:
Hmm, I can rework the regexp (it would still be icky), but it's not going to
help with the issue I don't think. I would prefer to not spam another prefix,
which is the only other way I can see for dealing with this without duplicating
the test, but if the lack of love is extreme I can probably go that way.
https://github.com/llvm/llvm-project/pull/88182
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[clang] [llvm] [mlir] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
@@ -1,14 +1,17 @@ // RUN: %clang_cc1 %s -triple=amdgcn-amd-amdhsa -std=c++11 -emit-llvm -o %t.ll -O1 -disable-llvm-passes -fms-extensions -fstrict-vtable-pointers +// RUN: %clang_cc1 %s -triple i686-pc-win32 -emit-llvm -o %t.ms.ll -O1 -disable-llvm-passes -fms-extensions -fstrict-vtable-pointers +// RUN: %clang_cc1 %s -triple=spirv64-unknown-unknown -fsycl-is-device -std=c++11 -emit-llvm -o %t.ll -O1 -disable-llvm-passes -fms-extensions -fstrict-vtable-pointers // FIXME: Assume load should not require -fstrict-vtable-pointers // RUN: FileCheck --check-prefix=CHECK1 --input-file=%t.ll %s // RUN: FileCheck --check-prefix=CHECK2 --input-file=%t.ll %s // RUN: FileCheck --check-prefix=CHECK3 --input-file=%t.ll %s // RUN: FileCheck --check-prefix=CHECK4 --input-file=%t.ll %s -// RUN: FileCheck --check-prefix=CHECK5 --input-file=%t.ll %s +// RUN: FileCheck --check-prefix=CHECK-MS --input-file=%t.ms.ll %s // RUN: FileCheck --check-prefix=CHECK6 --input-file=%t.ll %s // RUN: FileCheck --check-prefix=CHECK7 --input-file=%t.ll %s // RUN: FileCheck --check-prefix=CHECK8 --input-file=%t.ll %s +// RUN: FileCheck --check-prefix=CHECK9 --input-file=%t.ll %s AlexVlx wrote: Ah, the renumbering is a consequence of merging in the base `vtable-assume-load.cpp` test; initially when I "wrote" this one, I had removed the `CHECK-MS` case, which just made it look awkward when compared with the base, as @arichardson pointed out in another comment, so I merely brought that back in so that it looks less odd when comparing with the base case. Apologies for the noise. https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx commented: > Would be good to fold > clang/test/CodeGenCXX/vtable-assume-load-nonzero-default-address-space.cpp > into one of the files it was copied from, otherwise LGTM. Apologies for the delay, I was away; should be sorted now. https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
@@ -1370,7 +1370,7 @@ let IntrProperties = [IntrNoMem, IntrSpeculatable,
IntrWillReturn] in {
// The result of eh.typeid.for depends on the enclosing function, but inside a
// given function it is 'const' and may be CSE'd etc.
-def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
+def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty],
[IntrNoMem]>;
def int_eh_return_i32 : Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>;
AlexVlx wrote:
Possibly, but it's a slightly different matter which I should probably deal
with in another PR, wherein we handle the fact that the Program AS needn't be
0. AFAICT these intrinsics are here to support GCC's `__builtin_eh_return`, and
the pointer arg is supposed to point to a handler function in the Program AS. I
think it's preferable to handle that topic independently since it'll spawn its
own lively discussion, no doubt.
https://github.com/llvm/llvm-project/pull/88182
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[clang] [llvm] [mlir] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
@@ -0,0 +1,288 @@ +// RUN: %clang_cc1 %s -triple=spirv64-unknown-unknown -fsycl-is-device -std=c++11 -emit-llvm -o %t.ll -O1 -disable-llvm-passes -fms-extensions -fstrict-vtable-pointers +// FIXME: Assume load should not require -fstrict-vtable-pointers + +// RUN: FileCheck --check-prefix=CHECK1 --input-file=%t.ll %s AlexVlx wrote: If you do not mind, I will take it up as a subsequent activity, as I'd have to figure out the rationale of the test to see how to collapse it. For now, it would be nice to not tickle the dragon too much, this has already grown quite a bit beyond its initial state:) https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/7] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/Basic/Targets.cpp | 6 +-
clang/lib/Basic/Targets/SPIR.cpp | 288 +
clang/lib/Basic/Targets/SPIR.h| 51 +++
clang/lib/CodeGen/CGBuiltin.cpp | 7 +
clang/test/CodeGen/target-data.c | 4 +
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++
...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++
clang/test/CodeGenCUDA/long-double.cu | 4 +
clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129
.../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++
clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++
.../spirv-amdgcn-dpp-const-fold.hip | 46 +++
clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 +
.../predefined-macros-no-warnings.c | 1 +
clang/test/Preprocessor/predefined-macros.c | 10 +
...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++
.../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++
clang/test/SemaCUDA/allow-int128.cu | 3 +
clang/test/SemaCUDA/amdgpu-f128.cu| 1 +
clang/test/SemaCUDA/float16.cu| 1 +
clang/test/SemaCUDA/fp16-arg-return.cu| 1 +
.../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +
22 files changed, 1178 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
create mode 100644
clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip
create mode 100644
clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3283510c6aac7..04a13e3385d1f6 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const
llvm::Triple ,
}
case llvm::Triple::spirv64: {
if (os != llvm::Triple::UnknownOS ||
-Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
+ if (os == llvm::Triple::OSType::AMDHSA)
+return std::make_unique(Triple, Opts);
+
return nullptr;
+}
return std::make_unique(Triple, Opts);
}
case llvm::Triple::wasm32:
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index dc920177d3a910..d7d232ac9484f8 100644
--- a/clang/lib/Basic/Targets/SPIR.cpp
+++ b/clang/lib/Basic/Targets/SPIR.cpp
@@ -12,6 +12,8 @@
#include "SPIR.h"
#include "Targets.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
using namespace clang;
using namespace clang::targets;
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
\
+ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)
\
+ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#include "clang/Basic/BuiltinsAMDGPU.def"
+};
+
+namespace {
+const char *AMDGPUGCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+
[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
@@ -309,7 +309,45 @@ StringRef AMDGPU::getCanonicalArchName(const Triple ,
StringRef Arch) {
void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple ,
StringMap ) {
// XXX - What does the member GPU mean if device name string passed here?
- if (T.isAMDGCN()) {
+ if (T.isSPIRV() && T.getOS() == Triple::OSType::AMDHSA) {
+// AMDGCN SPIRV must support the union of all AMDGCN features.
+Features["atomic-ds-pk-add-16-insts"] = true;
+Features["atomic-flat-pk-add-16-insts"] = true;
+Features["atomic-buffer-global-pk-add-f16-insts"] = true;
+Features["atomic-global-pk-add-bf16-inst"] = true;
+Features["atomic-fadd-rtn-insts"] = true;
+Features["ci-insts"] = true;
+Features["dot1-insts"] = true;
+Features["dot2-insts"] = true;
+Features["dot3-insts"] = true;
+Features["dot4-insts"] = true;
+Features["dot5-insts"] = true;
+Features["dot7-insts"] = true;
+Features["dot8-insts"] = true;
+Features["dot9-insts"] = true;
+Features["dot10-insts"] = true;
+Features["dot11-insts"] = true;
+Features["dl-insts"] = true;
+Features["16-bit-insts"] = true;
+Features["dpp"] = true;
+Features["gfx8-insts"] = true;
+Features["gfx9-insts"] = true;
+Features["gfx90a-insts"] = true;
+Features["gfx940-insts"] = true;
+Features["gfx10-insts"] = true;
+Features["gfx10-3-insts"] = true;
+Features["gfx11-insts"] = true;
+Features["gfx12-insts"] = true;
AlexVlx wrote:
Yes, that is correct; the ME piece I mentioned will deal with avoiding spurious
errors such as a piece of dead code invoking a `gfx12` instruction when JITing
to a `gfx9` target, so that we only fail on actual misuses.
https://github.com/llvm/llvm-project/pull/89796
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[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
@@ -54,3 +56,76 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static const AMDGPUTargetInfo AMDGPUTI(llvm::Triple("amdgcn-amd-amdhsa"), {});
+
+ArrayRef SPIRV64AMDGCNTargetInfo::getGCCRegNames() const {
+ return AMDGPUTI.getGCCRegNames();
+}
+
+bool SPIRV64AMDGCNTargetInfo::initFeatureMap(
+llvm::StringMap , DiagnosticsEngine , StringRef,
+const std::vector ) const {
+ llvm::AMDGPU::fillAMDGPUFeatureMap({}, getTriple(), Features);
+
+ return TargetInfo::initFeatureMap(Features, Diags, {}, FeatureVec);
+}
+
+bool SPIRV64AMDGCNTargetInfo::validateAsmConstraint(
+const char *, TargetInfo::ConstraintInfo ) const {
+ return AMDGPUTI.validateAsmConstraint(Name, Info);
+}
+
+std::string
+SPIRV64AMDGCNTargetInfo::convertConstraint(const char *) const {
+ return AMDGPUTI.convertConstraint(Constraint);
+}
+
+ArrayRef SPIRV64AMDGCNTargetInfo::getTargetBuiltins() const {
+ return AMDGPUTI.getTargetBuiltins();
+}
+
+void SPIRV64AMDGCNTargetInfo::getTargetDefines(const LangOptions ,
+ MacroBuilder ) const {
+ BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
+ DefineStd(Builder, "SPIRV64", Opts);
+
+ Builder.defineMacro("__AMD__");
+ Builder.defineMacro("__AMDGPU__");
+ Builder.defineMacro("__AMDGCN__");
AlexVlx wrote:
`__AMDGCN_WAVEFRONT_SIZE` is a pretty terrible error, which should never have
been defined on host (not in the least because it's non-uniform across
targets). These do (should) end up defined on host too, but they are harmless
because they are uniform i.e. all potential consumers of `spirv64-amd-amdhsa`
are `__AMD__`, `__AMDGPU__` and `__AMDGCN__`. They're mostly a necessary
nuisance for getting library code to work.
https://github.com/llvm/llvm-project/pull/89796
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[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
@@ -309,7 +309,45 @@ StringRef AMDGPU::getCanonicalArchName(const Triple ,
StringRef Arch) {
void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple ,
StringMap ) {
// XXX - What does the member GPU mean if device name string passed here?
- if (T.isAMDGCN()) {
+ if (T.isSPIRV() && T.getOS() == Triple::OSType::AMDHSA) {
+// AMDGCN SPIRV must support the union of all AMDGCN features.
+Features["atomic-ds-pk-add-16-insts"] = true;
+Features["atomic-flat-pk-add-16-insts"] = true;
+Features["atomic-buffer-global-pk-add-f16-insts"] = true;
+Features["atomic-global-pk-add-bf16-inst"] = true;
+Features["atomic-fadd-rtn-insts"] = true;
+Features["ci-insts"] = true;
+Features["dot1-insts"] = true;
+Features["dot2-insts"] = true;
+Features["dot3-insts"] = true;
+Features["dot4-insts"] = true;
+Features["dot5-insts"] = true;
+Features["dot7-insts"] = true;
+Features["dot8-insts"] = true;
+Features["dot9-insts"] = true;
+Features["dot10-insts"] = true;
+Features["dot11-insts"] = true;
+Features["dl-insts"] = true;
+Features["16-bit-insts"] = true;
+Features["dpp"] = true;
+Features["gfx8-insts"] = true;
+Features["gfx9-insts"] = true;
+Features["gfx90a-insts"] = true;
+Features["gfx940-insts"] = true;
+Features["gfx10-insts"] = true;
+Features["gfx10-3-insts"] = true;
+Features["gfx11-insts"] = true;
+Features["gfx12-insts"] = true;
AlexVlx wrote:
One can neither say it's available nor say it's not, it's undecidable at SPIRV
generation time (if we knew, we'd not need it in the first place and would've
just targeted the actual hardware). The idea is that AMDGCN SPIRV will
"support" the union of AMDGCN features, so that the associated builtins /
constructs are retained in the generated SPIRV. Afterwards, at JIT time, one
handles matching to the actual physical target that is present; this is done
via a piece of paired functionality in the ME which has not yet been submitted.
https://github.com/llvm/llvm-project/pull/89796
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[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
@@ -6088,6 +6088,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
StringRef Prefix =
llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch());
if (!Prefix.empty()) {
+if (Prefix == "spv" &&
+getTarget().getTriple().getOS() == llvm::Triple::OSType::AMDHSA)
+ Prefix = "amdgcn";
AlexVlx wrote:
I don't think we can, with the current signature of that interface / the
current approach of keeping `spirv64` as the prefix, since we need at least the
OS type as well to disambiguate. So it'd require either overloading that
interface, or using a different prefix (this'd ripple elsewhere).
https://github.com/llvm/llvm-project/pull/89796
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[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
@@ -6088,6 +6088,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
StringRef Prefix =
llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch());
if (!Prefix.empty()) {
+if (Prefix == "spv" &&
+getTarget().getTriple().getOS() == llvm::Triple::OSType::AMDHSA)
+ Prefix = "amdgcn";
AlexVlx wrote:
I don't quite see any other point to tweak the logic. We have some `amdgcn`
builtins that get handled here, as opposed to via `EmitTargetBuiltinExpr`, and
this is the narrowest scope for adjusting `Prefix`; the information that this
is coming from AMDGCN flavoured SPIRV is lost past this point. Did you have
something in mind regarding where to handle this as an alternative?
https://github.com/llvm/llvm-project/pull/89796
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[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/6] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/Basic/Targets.cpp | 6 +-
clang/lib/Basic/Targets/SPIR.cpp | 288 +
clang/lib/Basic/Targets/SPIR.h| 51 +++
clang/lib/CodeGen/CGBuiltin.cpp | 7 +
clang/test/CodeGen/target-data.c | 4 +
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++
...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++
clang/test/CodeGenCUDA/long-double.cu | 4 +
clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129
.../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++
clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++
.../spirv-amdgcn-dpp-const-fold.hip | 46 +++
clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 +
.../predefined-macros-no-warnings.c | 1 +
clang/test/Preprocessor/predefined-macros.c | 10 +
...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++
.../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++
clang/test/SemaCUDA/allow-int128.cu | 3 +
clang/test/SemaCUDA/amdgpu-f128.cu| 1 +
clang/test/SemaCUDA/float16.cu| 1 +
clang/test/SemaCUDA/fp16-arg-return.cu| 1 +
.../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +
22 files changed, 1178 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
create mode 100644
clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip
create mode 100644
clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3283510c6aac7..04a13e3385d1f6 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const
llvm::Triple ,
}
case llvm::Triple::spirv64: {
if (os != llvm::Triple::UnknownOS ||
-Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
+ if (os == llvm::Triple::OSType::AMDHSA)
+return std::make_unique(Triple, Opts);
+
return nullptr;
+}
return std::make_unique(Triple, Opts);
}
case llvm::Triple::wasm32:
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index dc920177d3a910..d7d232ac9484f8 100644
--- a/clang/lib/Basic/Targets/SPIR.cpp
+++ b/clang/lib/Basic/Targets/SPIR.cpp
@@ -12,6 +12,8 @@
#include "SPIR.h"
#include "Targets.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
using namespace clang;
using namespace clang::targets;
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
\
+ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)
\
+ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#include "clang/Basic/BuiltinsAMDGPU.def"
+};
+
+namespace {
+const char *AMDGPUGCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+
[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
@@ -54,3 +56,77 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+namespace {
+const AMDGPUTargetInfo AMDGPUTI(llvm::Triple("amdgcn-amd-amdhsa"), {});
+
+} // anonymous namespace
+
+ArrayRef SPIRV64AMDGCNTargetInfo::getGCCRegNames() const {
+ return AMDGPUTI.getGCCRegNames();
+}
+
+bool SPIRV64AMDGCNTargetInfo::initFeatureMap(
+llvm::StringMap , DiagnosticsEngine , StringRef,
+const std::vector ) const {
+ llvm::AMDGPU::fillAMDGPUFeatureMap({}, getTriple(), Features);
+
+ return TargetInfo::initFeatureMap(Features, Diags, {}, FeatureVec);
+}
+
+bool SPIRV64AMDGCNTargetInfo::validateAsmConstraint(
+const char *, TargetInfo::ConstraintInfo ) const {
+ return AMDGPUTI.validateAsmConstraint(Name, Info);
+}
+
+std::string
+SPIRV64AMDGCNTargetInfo::convertConstraint(const char *) const {
+ return AMDGPUTI.convertConstraint(Constraint);
+}
+
+ArrayRef SPIRV64AMDGCNTargetInfo::getTargetBuiltins() const {
+ return AMDGPUTI.getTargetBuiltins();
+}
+
+void SPIRV64AMDGCNTargetInfo::getTargetDefines(const LangOptions ,
+ MacroBuilder ) const {
+ BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
+ DefineStd(Builder, "SPIRV64", Opts);
+
+ Builder.defineMacro("__AMD__");
+ Builder.defineMacro("__AMDGPU__");
+ Builder.defineMacro("__AMDGCN__");
+}
+
+void SPIRV64AMDGCNTargetInfo::setAuxTarget(const TargetInfo *Aux) {
AlexVlx wrote:
As far as I can tell, `setAuxTarget` is only used when compiling for CUDA /
HIP, and wouldn't get invoked otherwise (I could be wrong though); having said
that, it probably makes sense to assert that `Aux` is non-null, thanks for
pointing this out.
https://github.com/llvm/llvm-project/pull/89796
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[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/5] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/Basic/Targets.cpp | 6 +-
clang/lib/Basic/Targets/SPIR.cpp | 288 +
clang/lib/Basic/Targets/SPIR.h| 51 +++
clang/lib/CodeGen/CGBuiltin.cpp | 7 +
clang/test/CodeGen/target-data.c | 4 +
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++
...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++
clang/test/CodeGenCUDA/long-double.cu | 4 +
clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129
.../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++
clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++
.../spirv-amdgcn-dpp-const-fold.hip | 46 +++
clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 +
.../predefined-macros-no-warnings.c | 1 +
clang/test/Preprocessor/predefined-macros.c | 10 +
...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++
.../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++
clang/test/SemaCUDA/allow-int128.cu | 3 +
clang/test/SemaCUDA/amdgpu-f128.cu| 1 +
clang/test/SemaCUDA/float16.cu| 1 +
clang/test/SemaCUDA/fp16-arg-return.cu| 1 +
.../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +
22 files changed, 1178 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
create mode 100644
clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip
create mode 100644
clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3283510c6aac7..04a13e3385d1f6 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const
llvm::Triple ,
}
case llvm::Triple::spirv64: {
if (os != llvm::Triple::UnknownOS ||
-Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
+ if (os == llvm::Triple::OSType::AMDHSA)
+return std::make_unique(Triple, Opts);
+
return nullptr;
+}
return std::make_unique(Triple, Opts);
}
case llvm::Triple::wasm32:
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index dc920177d3a910..d7d232ac9484f8 100644
--- a/clang/lib/Basic/Targets/SPIR.cpp
+++ b/clang/lib/Basic/Targets/SPIR.cpp
@@ -12,6 +12,8 @@
#include "SPIR.h"
#include "Targets.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
using namespace clang;
using namespace clang::targets;
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
\
+ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)
\
+ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#include "clang/Basic/BuiltinsAMDGPU.def"
+};
+
+namespace {
+const char *AMDGPUGCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+
[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/4] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/Basic/Targets.cpp | 6 +-
clang/lib/Basic/Targets/SPIR.cpp | 288 +
clang/lib/Basic/Targets/SPIR.h| 51 +++
clang/lib/CodeGen/CGBuiltin.cpp | 7 +
clang/test/CodeGen/target-data.c | 4 +
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++
...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++
clang/test/CodeGenCUDA/long-double.cu | 4 +
clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129
.../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++
clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++
.../spirv-amdgcn-dpp-const-fold.hip | 46 +++
clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 +
.../predefined-macros-no-warnings.c | 1 +
clang/test/Preprocessor/predefined-macros.c | 10 +
...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++
.../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++
clang/test/SemaCUDA/allow-int128.cu | 3 +
clang/test/SemaCUDA/amdgpu-f128.cu| 1 +
clang/test/SemaCUDA/float16.cu| 1 +
clang/test/SemaCUDA/fp16-arg-return.cu| 1 +
.../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +
22 files changed, 1178 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
create mode 100644
clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip
create mode 100644
clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3283510c6aac7..04a13e3385d1f6 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const
llvm::Triple ,
}
case llvm::Triple::spirv64: {
if (os != llvm::Triple::UnknownOS ||
-Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
+ if (os == llvm::Triple::OSType::AMDHSA)
+return std::make_unique(Triple, Opts);
+
return nullptr;
+}
return std::make_unique(Triple, Opts);
}
case llvm::Triple::wasm32:
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index dc920177d3a910..d7d232ac9484f8 100644
--- a/clang/lib/Basic/Targets/SPIR.cpp
+++ b/clang/lib/Basic/Targets/SPIR.cpp
@@ -12,6 +12,8 @@
#include "SPIR.h"
#include "Targets.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
using namespace clang;
using namespace clang::targets;
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
\
+ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)
\
+ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#include "clang/Basic/BuiltinsAMDGPU.def"
+};
+
+namespace {
+const char *AMDGPUGCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+
[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
@@ -0,0 +1,294 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip \ +// RUN: -aux-triple x86_64-unknown-linux-gnu -fcuda-is-device -emit-llvm %s \ +// RUN: -o - | FileCheck %s + +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip \ +// RUN: -aux-triple x86_64-pc-windows-msvc -fcuda-is-device -emit-llvm %s \ +// RUN: -o - | FileCheck %s + +#include "Inputs/cuda.h" + AlexVlx wrote: Done. https://github.com/llvm/llvm-project/pull/89796 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/4] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/Basic/Targets.cpp | 6 +-
clang/lib/Basic/Targets/SPIR.cpp | 288 +
clang/lib/Basic/Targets/SPIR.h| 51 +++
clang/lib/CodeGen/CGBuiltin.cpp | 7 +
clang/test/CodeGen/target-data.c | 4 +
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++
...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++
clang/test/CodeGenCUDA/long-double.cu | 4 +
clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129
.../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++
clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++
.../spirv-amdgcn-dpp-const-fold.hip | 46 +++
clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 +
.../predefined-macros-no-warnings.c | 1 +
clang/test/Preprocessor/predefined-macros.c | 10 +
...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++
.../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++
clang/test/SemaCUDA/allow-int128.cu | 3 +
clang/test/SemaCUDA/amdgpu-f128.cu| 1 +
clang/test/SemaCUDA/float16.cu| 1 +
clang/test/SemaCUDA/fp16-arg-return.cu| 1 +
.../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +
22 files changed, 1178 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
create mode 100644
clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip
create mode 100644
clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3283510c6aac7..04a13e3385d1f6 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const
llvm::Triple ,
}
case llvm::Triple::spirv64: {
if (os != llvm::Triple::UnknownOS ||
-Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
+ if (os == llvm::Triple::OSType::AMDHSA)
+return std::make_unique(Triple, Opts);
+
return nullptr;
+}
return std::make_unique(Triple, Opts);
}
case llvm::Triple::wasm32:
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index dc920177d3a910..d7d232ac9484f8 100644
--- a/clang/lib/Basic/Targets/SPIR.cpp
+++ b/clang/lib/Basic/Targets/SPIR.cpp
@@ -12,6 +12,8 @@
#include "SPIR.h"
#include "Targets.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
using namespace clang;
using namespace clang::targets;
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
\
+ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)
\
+ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#include "clang/Basic/BuiltinsAMDGPU.def"
+};
+
+namespace {
+const char *AMDGPUGCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+
[clang] [llvm] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/3] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/Basic/Targets.cpp | 6 +-
clang/lib/Basic/Targets/SPIR.cpp | 288 +
clang/lib/Basic/Targets/SPIR.h| 51 +++
clang/lib/CodeGen/CGBuiltin.cpp | 7 +
clang/test/CodeGen/target-data.c | 4 +
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++
...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++
clang/test/CodeGenCUDA/long-double.cu | 4 +
clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129
.../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++
clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++
.../spirv-amdgcn-dpp-const-fold.hip | 46 +++
clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 +
.../predefined-macros-no-warnings.c | 1 +
clang/test/Preprocessor/predefined-macros.c | 10 +
...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++
.../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++
clang/test/SemaCUDA/allow-int128.cu | 3 +
clang/test/SemaCUDA/amdgpu-f128.cu| 1 +
clang/test/SemaCUDA/float16.cu| 1 +
clang/test/SemaCUDA/fp16-arg-return.cu| 1 +
.../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +
22 files changed, 1178 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
create mode 100644
clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip
create mode 100644
clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3283510c6aac7..04a13e3385d1f6 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const
llvm::Triple ,
}
case llvm::Triple::spirv64: {
if (os != llvm::Triple::UnknownOS ||
-Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
+ if (os == llvm::Triple::OSType::AMDHSA)
+return std::make_unique(Triple, Opts);
+
return nullptr;
+}
return std::make_unique(Triple, Opts);
}
case llvm::Triple::wasm32:
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index dc920177d3a910..d7d232ac9484f8 100644
--- a/clang/lib/Basic/Targets/SPIR.cpp
+++ b/clang/lib/Basic/Targets/SPIR.cpp
@@ -12,6 +12,8 @@
#include "SPIR.h"
#include "Targets.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
using namespace clang;
using namespace clang::targets;
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
\
+ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)
\
+ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#include "clang/Basic/BuiltinsAMDGPU.def"
+};
+
+namespace {
+const char *AMDGPUGCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+
[clang] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/2] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/Basic/Targets.cpp | 6 +-
clang/lib/Basic/Targets/SPIR.cpp | 288 +
clang/lib/Basic/Targets/SPIR.h| 51 +++
clang/lib/CodeGen/CGBuiltin.cpp | 7 +
clang/test/CodeGen/target-data.c | 4 +
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++
...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++
clang/test/CodeGenCUDA/long-double.cu | 4 +
clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129
.../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++
clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++
.../spirv-amdgcn-dpp-const-fold.hip | 46 +++
clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 +
.../predefined-macros-no-warnings.c | 1 +
clang/test/Preprocessor/predefined-macros.c | 10 +
...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++
.../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++
clang/test/SemaCUDA/allow-int128.cu | 3 +
clang/test/SemaCUDA/amdgpu-f128.cu| 1 +
clang/test/SemaCUDA/float16.cu| 1 +
clang/test/SemaCUDA/fp16-arg-return.cu| 1 +
.../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +
22 files changed, 1178 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
create mode 100644
clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip
create mode 100644
clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3283510c6aac7..04a13e3385d1f6 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const
llvm::Triple ,
}
case llvm::Triple::spirv64: {
if (os != llvm::Triple::UnknownOS ||
-Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
+ if (os == llvm::Triple::OSType::AMDHSA)
+return std::make_unique(Triple, Opts);
+
return nullptr;
+}
return std::make_unique(Triple, Opts);
}
case llvm::Triple::wasm32:
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index dc920177d3a910..d7d232ac9484f8 100644
--- a/clang/lib/Basic/Targets/SPIR.cpp
+++ b/clang/lib/Basic/Targets/SPIR.cpp
@@ -12,6 +12,8 @@
#include "SPIR.h"
#include "Targets.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
using namespace clang;
using namespace clang::targets;
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
\
+ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)
\
+ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#include "clang/Basic/BuiltinsAMDGPU.def"
+};
+
+namespace {
+const char *AMDGPUGCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+
[clang] [llvm] [mlir] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
@@ -2216,7 +2216,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
AlexVlx wrote:
It could be `GlobalsInt8PtrTy`, but the main roadblock would require something
that @rjmccall suggested looking into, namely adding the ability to declare a
default AS for a class type, which stdlib implementations could then re-use.
Having said that, I've neither had the time to look into it, nor figured out if
this would work in general, considering we need to compose with stdlib
implementations other than libc++. Having said that, perhaps the TODO: should
actually be at the end of the comment, and just say something along the lines
of "investigate if it is possible to remove this limitation"?
https://github.com/llvm/llvm-project/pull/88182
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx commented: > This adds a third copy of the same test, can we just merge them add add three > RUN lines with different CHECK prefixes? I've merged the address-space related ones, but I've left the basic one in place. https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 01/10] Start migrating away from the embedded assumption that
the default AS **must** be 0.
---
clang/lib/CodeGen/CGExprCXX.cpp | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 10 ++
clang/lib/CodeGen/CodeGenTypeCache.h | 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 2adbef6d55122c..b9c920a81d79c9 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -,7 +,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
LangAS GlobAS = CGM.GetGlobalVarAddressSpace(nullptr);
auto MaybeASCast = [=](auto &) {
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 8ceecff28cbc63..7dd14d32aa2d03 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -364,7 +364,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
IntTy = llvm::IntegerType::get(LLVMContext, C.getTargetInfo().getIntWidth());
IntPtrTy = llvm::IntegerType::get(LLVMContext,
C.getTargetInfo().getMaxPointerWidth());
- Int8PtrTy = llvm::PointerType::get(LLVMContext, 0);
+ Int8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetInfo().getTargetAddressSpace(LangAS::Default));
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
@@ -4512,9 +4513,10 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction(
IsIncompleteFunction = true;
}
- llvm::Function *F =
- llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, ());
+ llvm::Function *F = llvm::Function::Create(
+ FTy, llvm::Function::ExternalLinkage,
+ getDataLayout().getProgramAddressSpace(),
+ Entry ? StringRef() : MangledName, ());
// Store the declaration associated with this function so it is potentially
// updated by further declarations or definitions and emitted at the end.
diff --git a/clang/lib/CodeGen/CodeGenTypeCache.h
b/clang/lib/CodeGen/CodeGenTypeCache.h
index 083d69214fb3c2..e273ebe3b060f2 100644
--- a/clang/lib/CodeGen/CodeGenTypeCache.h
+++ b/clang/lib/CodeGen/CodeGenTypeCache.h
@@ -51,7 +51,7 @@ struct CodeGenTypeCache {
llvm::IntegerType *PtrDiffTy;
};
- /// void*, void** in address space 0
+ /// void*, void** in the target's default address space (often 0)
union {
llvm::PointerType *UnqualPtrTy;
llvm::PointerType *VoidPtrTy;
>From 74ae6f52a5f84f8fc92135df3ff93a4a89b914ed Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 25 Mar 2024 10:55:22 +0200
Subject: [PATCH 02/10] Make querying the Global AS more robust, add 1 new test
(WiP).
---
clang/lib/CodeGen/CodeGenModule.cpp | 10 ---
clang/lib/CodeGen/ItaniumCXXABI.cpp | 4 ++-
...x11-with-nonzero-default-address-space.cpp | 29 +++
3 files changed, 38 insertions(+), 5 deletions(-)
create mode 100644
clang/test/CodeGenCXX/typeid-cxx11-with-nonzero-default-address-space.cpp
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 63d54f9b1c0b60..39ccd40bf1adbb 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -371,8 +371,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
- GlobalsInt8PtrTy =
- llvm::PointerType::get(LLVMContext, DL.getDefaultGlobalsAddressSpace());
+ GlobalsInt8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetAddressSpace(GetGlobalVarAddressSpace(nullptr)));
ConstGlobalsPtrTy = llvm::PointerType::get(
LLVMContext, C.getTargetAddressSpace(GetGlobalConstantAddressSpace()));
ASTAllocaAddressSpace = getTargetCodeGenInfo().getASTAllocaAddressSpace();
@@ -5018,7 +5018,9 @@ llvm::GlobalVariable
*CodeGenModule::CreateOrReplaceCXXRuntimeVariable(
// Create a new variable.
GV = new llvm::GlobalVariable(getModule(), Ty, /*isConstant=*/true,
-Linkage, nullptr, Name);
+Linkage, nullptr, Name, nullptr,
+llvm::GlobalValue::NotThreadLocal,
+GlobalsInt8PtrTy->getAddressSpace());
if (OldGV) {
// Replace occurrences of the old variable if needed.
@@ -5133,7 +5135,7 @@ LangAS
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
@@ -2216,7 +2216,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
AlexVlx wrote:
Done-ish, please let me know if this is not actually helpful in clarifying and
I can refine / reword.
https://github.com/llvm/llvm-project/pull/88182
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/9] Start migrating away from the embedded assumption that
the default AS **must** be 0.
---
clang/lib/CodeGen/CGExprCXX.cpp | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 10 ++
clang/lib/CodeGen/CodeGenTypeCache.h | 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 2adbef6d55122c..b9c920a81d79c9 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -,7 +,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
LangAS GlobAS = CGM.GetGlobalVarAddressSpace(nullptr);
auto MaybeASCast = [=](auto &) {
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 8ceecff28cbc63..7dd14d32aa2d03 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -364,7 +364,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
IntTy = llvm::IntegerType::get(LLVMContext, C.getTargetInfo().getIntWidth());
IntPtrTy = llvm::IntegerType::get(LLVMContext,
C.getTargetInfo().getMaxPointerWidth());
- Int8PtrTy = llvm::PointerType::get(LLVMContext, 0);
+ Int8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetInfo().getTargetAddressSpace(LangAS::Default));
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
@@ -4512,9 +4513,10 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction(
IsIncompleteFunction = true;
}
- llvm::Function *F =
- llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, ());
+ llvm::Function *F = llvm::Function::Create(
+ FTy, llvm::Function::ExternalLinkage,
+ getDataLayout().getProgramAddressSpace(),
+ Entry ? StringRef() : MangledName, ());
// Store the declaration associated with this function so it is potentially
// updated by further declarations or definitions and emitted at the end.
diff --git a/clang/lib/CodeGen/CodeGenTypeCache.h
b/clang/lib/CodeGen/CodeGenTypeCache.h
index 083d69214fb3c2..e273ebe3b060f2 100644
--- a/clang/lib/CodeGen/CodeGenTypeCache.h
+++ b/clang/lib/CodeGen/CodeGenTypeCache.h
@@ -51,7 +51,7 @@ struct CodeGenTypeCache {
llvm::IntegerType *PtrDiffTy;
};
- /// void*, void** in address space 0
+ /// void*, void** in the target's default address space (often 0)
union {
llvm::PointerType *UnqualPtrTy;
llvm::PointerType *VoidPtrTy;
>From 74ae6f52a5f84f8fc92135df3ff93a4a89b914ed Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 25 Mar 2024 10:55:22 +0200
Subject: [PATCH 2/9] Make querying the Global AS more robust, add 1 new test
(WiP).
---
clang/lib/CodeGen/CodeGenModule.cpp | 10 ---
clang/lib/CodeGen/ItaniumCXXABI.cpp | 4 ++-
...x11-with-nonzero-default-address-space.cpp | 29 +++
3 files changed, 38 insertions(+), 5 deletions(-)
create mode 100644
clang/test/CodeGenCXX/typeid-cxx11-with-nonzero-default-address-space.cpp
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 63d54f9b1c0b60..39ccd40bf1adbb 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -371,8 +371,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
- GlobalsInt8PtrTy =
- llvm::PointerType::get(LLVMContext, DL.getDefaultGlobalsAddressSpace());
+ GlobalsInt8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetAddressSpace(GetGlobalVarAddressSpace(nullptr)));
ConstGlobalsPtrTy = llvm::PointerType::get(
LLVMContext, C.getTargetAddressSpace(GetGlobalConstantAddressSpace()));
ASTAllocaAddressSpace = getTargetCodeGenInfo().getASTAllocaAddressSpace();
@@ -5018,7 +5018,9 @@ llvm::GlobalVariable
*CodeGenModule::CreateOrReplaceCXXRuntimeVariable(
// Create a new variable.
GV = new llvm::GlobalVariable(getModule(), Ty, /*isConstant=*/true,
-Linkage, nullptr, Name);
+Linkage, nullptr, Name, nullptr,
+llvm::GlobalValue::NotThreadLocal,
+GlobalsInt8PtrTy->getAddressSpace());
if (OldGV) {
// Replace occurrences of the old variable if needed.
@@ -5133,7 +5135,7 @@ LangAS
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/8] Start migrating away from the embedded assumption that
the default AS **must** be 0.
---
clang/lib/CodeGen/CGExprCXX.cpp | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 10 ++
clang/lib/CodeGen/CodeGenTypeCache.h | 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 2adbef6d55122c..b9c920a81d79c9 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -,7 +,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
LangAS GlobAS = CGM.GetGlobalVarAddressSpace(nullptr);
auto MaybeASCast = [=](auto &) {
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 8ceecff28cbc63..7dd14d32aa2d03 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -364,7 +364,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
IntTy = llvm::IntegerType::get(LLVMContext, C.getTargetInfo().getIntWidth());
IntPtrTy = llvm::IntegerType::get(LLVMContext,
C.getTargetInfo().getMaxPointerWidth());
- Int8PtrTy = llvm::PointerType::get(LLVMContext, 0);
+ Int8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetInfo().getTargetAddressSpace(LangAS::Default));
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
@@ -4512,9 +4513,10 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction(
IsIncompleteFunction = true;
}
- llvm::Function *F =
- llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, ());
+ llvm::Function *F = llvm::Function::Create(
+ FTy, llvm::Function::ExternalLinkage,
+ getDataLayout().getProgramAddressSpace(),
+ Entry ? StringRef() : MangledName, ());
// Store the declaration associated with this function so it is potentially
// updated by further declarations or definitions and emitted at the end.
diff --git a/clang/lib/CodeGen/CodeGenTypeCache.h
b/clang/lib/CodeGen/CodeGenTypeCache.h
index 083d69214fb3c2..e273ebe3b060f2 100644
--- a/clang/lib/CodeGen/CodeGenTypeCache.h
+++ b/clang/lib/CodeGen/CodeGenTypeCache.h
@@ -51,7 +51,7 @@ struct CodeGenTypeCache {
llvm::IntegerType *PtrDiffTy;
};
- /// void*, void** in address space 0
+ /// void*, void** in the target's default address space (often 0)
union {
llvm::PointerType *UnqualPtrTy;
llvm::PointerType *VoidPtrTy;
>From 74ae6f52a5f84f8fc92135df3ff93a4a89b914ed Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 25 Mar 2024 10:55:22 +0200
Subject: [PATCH 2/8] Make querying the Global AS more robust, add 1 new test
(WiP).
---
clang/lib/CodeGen/CodeGenModule.cpp | 10 ---
clang/lib/CodeGen/ItaniumCXXABI.cpp | 4 ++-
...x11-with-nonzero-default-address-space.cpp | 29 +++
3 files changed, 38 insertions(+), 5 deletions(-)
create mode 100644
clang/test/CodeGenCXX/typeid-cxx11-with-nonzero-default-address-space.cpp
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 63d54f9b1c0b60..39ccd40bf1adbb 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -371,8 +371,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
- GlobalsInt8PtrTy =
- llvm::PointerType::get(LLVMContext, DL.getDefaultGlobalsAddressSpace());
+ GlobalsInt8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetAddressSpace(GetGlobalVarAddressSpace(nullptr)));
ConstGlobalsPtrTy = llvm::PointerType::get(
LLVMContext, C.getTargetAddressSpace(GetGlobalConstantAddressSpace()));
ASTAllocaAddressSpace = getTargetCodeGenInfo().getASTAllocaAddressSpace();
@@ -5018,7 +5018,9 @@ llvm::GlobalVariable
*CodeGenModule::CreateOrReplaceCXXRuntimeVariable(
// Create a new variable.
GV = new llvm::GlobalVariable(getModule(), Ty, /*isConstant=*/true,
-Linkage, nullptr, Name);
+Linkage, nullptr, Name, nullptr,
+llvm::GlobalValue::NotThreadLocal,
+GlobalsInt8PtrTy->getAddressSpace());
if (OldGV) {
// Replace occurrences of the old variable if needed.
@@ -5133,7 +5135,7 @@ LangAS
[clang] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
AlexVlx wrote: > > > How much of this is actually different from the existing target info for > > > AMDGCN? Seems like we're doing a lot of redundant stuff like defining > > > macros or features. > > > > > > That's part of the point, it's not actually supposed to differ in those > > particular regards, up to the point where things fork into specific GFXIPs. > > At the same time, there's no feasible way to re-use any of that, at least > > not one that I can see with how targets currently work. If you're > > suggesting that this should actually be based on AMDGPUTargetInfo, that's > > probably not the right way to go since that sets additional things that do > > not work with SPIRV at all. > > Yeah, I was unsure how much of this is a subset. We could pull the common > stuff into some new base class that both targets then inherit from, but it > depends how much code we actually save with that method. I think I agree at > the very least we should try to avoid duplicating the register list. That's not a bad idea but I *suspect* we'll run into a physical design issue since there doesn't seem to be a natural place to put the shared base - unless you were thinking about a place in particular? We'd probably have to relocate this to the AMDGCN side, and then duplicate the SPIRV bits/details, and at that point we could just re-use/share the reg defs. https://github.com/llvm/llvm-project/pull/89796 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
\
+ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)
\
+ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#include "clang/Basic/BuiltinsAMDGPU.def"
+};
+
+namespace {
+const char *AMDGPUGCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+ "v126", "v127", "v128", "v129", "v130", "v131", "v132", "v133", "v134",
+ "v135", "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
+ "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", "v152",
+ "v153", "v154", "v155", "v156", "v157", "v158", "v159", "v160", "v161",
+ "v162", "v163", "v164", "v165", "v166", "v167", "v168", "v169", "v170",
+ "v171", "v172", "v173", "v174", "v175", "v176", "v177", "v178", "v179",
+ "v180", "v181", "v182", "v183", "v184", "v185", "v186", "v187", "v188",
+ "v189", "v190", "v191", "v192", "v193", "v194", "v195", "v196", "v197",
+ "v198", "v199", "v200", "v201", "v202", "v203", "v204", "v205", "v206",
+ "v207", "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
+ "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", "v224",
+ "v225", "v226", "v227", "v228", "v229", "v230", "v231", "v232", "v233",
+ "v234", "v235", "v236", "v237", "v238", "v239", "v240", "v241", "v242",
+ "v243", "v244", "v245", "v246", "v247", "v248", "v249", "v250", "v251",
+ "v252", "v253", "v254", "v255", "s0", "s1", "s2", "s3", "s4",
+ "s5", "s6", "s7", "s8", "s9", "s10", "s11", "s12", "s13",
+ "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
+ "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
+ "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", "s40",
+ "s41", "s42", "s43", "s44", "s45", "s46", "s47", "s48", "s49",
+ "s50", "s51", "s52", "s53", "s54", "s55", "s56", "s57", "s58",
+ "s59", "s60", "s61", "s62", "s63", "s64", "s65", "s66", "s67",
+ "s68", "s69", "s70", "s71", "s72", "s73", "s74", "s75", "s76",
+ "s77", "s78", "s79", "s80", "s81", "s82", "s83", "s84", "s85",
+ "s86", "s87", "s88", "s89", "s90", "s91", "s92", "s93", "s94",
+ "s95", "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
+ "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", "s112",
+ "s113", "s114", "s115", "s116", "s117", "s118", "s119", "s120", "s121",
+ "s122", "s123", "s124", "s125", "s126", "s127", "exec", "vcc", "scc",
+ "m0", "flat_scratch", "exec_lo", "exec_hi", "vcc_lo", "vcc_hi",
+ "flat_scratch_lo", "flat_scratch_hi",
+ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8",
+ "a9", "a10", "a11", "a12", "a13", "a14", "a15", "a16", "a17",
+ "a18", "a19", "a20", "a21", "a22", "a23", "a24", "a25", "a26",
+ "a27", "a28", "a29", "a30", "a31", "a32", "a33", "a34", "a35",
+ "a36", "a37", "a38", "a39", "a40", "a41", "a42", "a43", "a44",
+ "a45", "a46", "a47", "a48", "a49", "a50", "a51", "a52", "a53",
+ "a54", "a55", "a56", "a57", "a58", "a59", "a60", "a61", "a62",
+ "a63", "a64", "a65", "a66", "a67", "a68", "a69", "a70", "a71",
+ "a72", "a73", "a74", "a75", "a76", "a77", "a78", "a79", "a80",
+ "a81", "a82", "a83", "a84", "a85", "a86", "a87", "a88", "a89",
+ "a90", "a91", "a92", "a93", "a94", "a95", "a96", "a97", "a98",
+ "a99", "a100", "a101", "a102", "a103", "a104", "a105", "a106", "a107",
+ "a108", "a109", "a110", "a111", "a112", "a113", "a114", "a115", "a116",
+ "a117", "a118", "a119", "a120", "a121", "a122", "a123", "a124", "a125",
+ "a126", "a127", "a128", "a129", "a130", "a131", "a132", "a133", "a134",
+ "a135", "a136", "a137", "a138", "a139", "a140", "a141", "a142", "a143",
+ "a144", "a145", "a146", "a147", "a148", "a149", "a150", "a151", "a152",
+ "a153", "a154", "a155", "a156", "a157", "a158", "a159",
[clang] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
AlexVlx wrote: > How much of this is actually different from the existing target info for > AMDGCN? Seems like we're doing a lot of redundant stuff like defining macros > or features. That's part of the point, it's not actually supposed to differ in those particular regards, up to the point where things fork into specific GFXIPs. At the same time, there's no feasible way to re-use any of that, at least not one that I can see with how targets currently work. If you're suggesting that this should actually be based on AMDGPUTargetInfo, that's probably not the right way to go since that sets additional things that do not work with SPIRV at all. https://github.com/llvm/llvm-project/pull/89796 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/8] Start migrating away from the embedded assumption that
the default AS **must** be 0.
---
clang/lib/CodeGen/CGExprCXX.cpp | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 10 ++
clang/lib/CodeGen/CodeGenTypeCache.h | 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 2adbef6d55122c..b9c920a81d79c9 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -,7 +,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
LangAS GlobAS = CGM.GetGlobalVarAddressSpace(nullptr);
auto MaybeASCast = [=](auto &) {
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 8ceecff28cbc63..7dd14d32aa2d03 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -364,7 +364,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
IntTy = llvm::IntegerType::get(LLVMContext, C.getTargetInfo().getIntWidth());
IntPtrTy = llvm::IntegerType::get(LLVMContext,
C.getTargetInfo().getMaxPointerWidth());
- Int8PtrTy = llvm::PointerType::get(LLVMContext, 0);
+ Int8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetInfo().getTargetAddressSpace(LangAS::Default));
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
@@ -4512,9 +4513,10 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction(
IsIncompleteFunction = true;
}
- llvm::Function *F =
- llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, ());
+ llvm::Function *F = llvm::Function::Create(
+ FTy, llvm::Function::ExternalLinkage,
+ getDataLayout().getProgramAddressSpace(),
+ Entry ? StringRef() : MangledName, ());
// Store the declaration associated with this function so it is potentially
// updated by further declarations or definitions and emitted at the end.
diff --git a/clang/lib/CodeGen/CodeGenTypeCache.h
b/clang/lib/CodeGen/CodeGenTypeCache.h
index 083d69214fb3c2..e273ebe3b060f2 100644
--- a/clang/lib/CodeGen/CodeGenTypeCache.h
+++ b/clang/lib/CodeGen/CodeGenTypeCache.h
@@ -51,7 +51,7 @@ struct CodeGenTypeCache {
llvm::IntegerType *PtrDiffTy;
};
- /// void*, void** in address space 0
+ /// void*, void** in the target's default address space (often 0)
union {
llvm::PointerType *UnqualPtrTy;
llvm::PointerType *VoidPtrTy;
>From 74ae6f52a5f84f8fc92135df3ff93a4a89b914ed Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 25 Mar 2024 10:55:22 +0200
Subject: [PATCH 2/8] Make querying the Global AS more robust, add 1 new test
(WiP).
---
clang/lib/CodeGen/CodeGenModule.cpp | 10 ---
clang/lib/CodeGen/ItaniumCXXABI.cpp | 4 ++-
...x11-with-nonzero-default-address-space.cpp | 29 +++
3 files changed, 38 insertions(+), 5 deletions(-)
create mode 100644
clang/test/CodeGenCXX/typeid-cxx11-with-nonzero-default-address-space.cpp
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 63d54f9b1c0b60..39ccd40bf1adbb 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -371,8 +371,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
- GlobalsInt8PtrTy =
- llvm::PointerType::get(LLVMContext, DL.getDefaultGlobalsAddressSpace());
+ GlobalsInt8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetAddressSpace(GetGlobalVarAddressSpace(nullptr)));
ConstGlobalsPtrTy = llvm::PointerType::get(
LLVMContext, C.getTargetAddressSpace(GetGlobalConstantAddressSpace()));
ASTAllocaAddressSpace = getTargetCodeGenInfo().getASTAllocaAddressSpace();
@@ -5018,7 +5018,9 @@ llvm::GlobalVariable
*CodeGenModule::CreateOrReplaceCXXRuntimeVariable(
// Create a new variable.
GV = new llvm::GlobalVariable(getModule(), Ty, /*isConstant=*/true,
-Linkage, nullptr, Name);
+Linkage, nullptr, Name, nullptr,
+llvm::GlobalValue::NotThreadLocal,
+GlobalsInt8PtrTy->getAddressSpace());
if (OldGV) {
// Replace occurrences of the old variable if needed.
@@ -5133,7 +5135,7 @@ LangAS
[clang] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/2] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/Basic/Targets.cpp | 6 +-
clang/lib/Basic/Targets/SPIR.cpp | 288 +
clang/lib/Basic/Targets/SPIR.h| 51 +++
clang/lib/CodeGen/CGBuiltin.cpp | 7 +
clang/test/CodeGen/target-data.c | 4 +
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++
...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++
clang/test/CodeGenCUDA/long-double.cu | 4 +
clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129
.../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++
clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++
.../spirv-amdgcn-dpp-const-fold.hip | 46 +++
clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 +
.../predefined-macros-no-warnings.c | 1 +
clang/test/Preprocessor/predefined-macros.c | 10 +
...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++
.../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++
clang/test/SemaCUDA/allow-int128.cu | 3 +
clang/test/SemaCUDA/amdgpu-f128.cu| 1 +
clang/test/SemaCUDA/float16.cu| 1 +
clang/test/SemaCUDA/fp16-arg-return.cu| 1 +
.../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +
22 files changed, 1178 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
create mode 100644
clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip
create mode 100644
clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3283510c6aac7..04a13e3385d1f6 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const
llvm::Triple ,
}
case llvm::Triple::spirv64: {
if (os != llvm::Triple::UnknownOS ||
-Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
+ if (os == llvm::Triple::OSType::AMDHSA)
+return std::make_unique(Triple, Opts);
+
return nullptr;
+}
return std::make_unique(Triple, Opts);
}
case llvm::Triple::wasm32:
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index dc920177d3a910..d7d232ac9484f8 100644
--- a/clang/lib/Basic/Targets/SPIR.cpp
+++ b/clang/lib/Basic/Targets/SPIR.cpp
@@ -12,6 +12,8 @@
#include "SPIR.h"
#include "Targets.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
using namespace clang;
using namespace clang::targets;
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
\
+ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)
\
+ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
+#include "clang/Basic/BuiltinsAMDGPU.def"
+};
+
+namespace {
+const char *AMDGPUGCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+
[clang] [clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (PR #89796)
https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/89796
This change seeks to add support for vendor flavoured SPIRV - more
specifically, AMDGCN flavoured SPIRV. The aim is to generate SPIRV that carries
some extra bits of information that are only usable by AMDGCN targets,
forfeiting absolute genericity to obtain greater expressiveness for target
features:
- AMDGCN inline ASM is allowed/supported, under the assumption that the
[SPV_INTEL_inline_assembly](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_inline_assembly.asciidoc)
extension is enabled/used
- AMDGCN target specific builtins are allowed/supported, under the assumption
that e.g. the `--spirv-allow-unknown-intrinsics` option is enabled when using
the downstream translator
- the featureset matches the union of AMDGCN targets' features
- the datalayout string is overspecified to affix both the program address
space and the alloca address space, the latter under the assumption that the
[SPV_INTEL_function_pointers](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_function_pointers.asciidoc)
extension is enabled/used, case in which the extant SPIRV datalayout string
would lead to pointers to function pointing to the private address space, which
would be wrong.
Existing AMDGCN tests are extended to cover this new target. It is currently
dormant / will require some additional changes, but I thought I'd rather put it
up for review to get feedback as early as possible. I will note that an
alternative option is to place this under AMDGPU, but that seems slightly less
natural, since this is still SPIRV, albeit relaxed in terms of preconditions &
constrained in terms of postconditions, and only guaranteed to be usable on
AMDGCN targets (it is still possible to obtain pristine portable SPIRV through
usage of the flavoured target, though).
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/Basic/Targets.cpp | 6 +-
clang/lib/Basic/Targets/SPIR.cpp | 288 +
clang/lib/Basic/Targets/SPIR.h| 51 +++
clang/lib/CodeGen/CGBuiltin.cpp | 7 +
clang/test/CodeGen/target-data.c | 4 +
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++
...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++
clang/test/CodeGenCUDA/long-double.cu | 4 +
clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129
.../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++
clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++
.../spirv-amdgcn-dpp-const-fold.hip | 46 +++
clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 +
.../predefined-macros-no-warnings.c | 1 +
clang/test/Preprocessor/predefined-macros.c | 10 +
...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++
.../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++
clang/test/SemaCUDA/allow-int128.cu | 3 +
clang/test/SemaCUDA/amdgpu-f128.cu| 1 +
clang/test/SemaCUDA/float16.cu| 1 +
clang/test/SemaCUDA/fp16-arg-return.cu| 1 +
.../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +
22 files changed, 1178 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
create mode 100644
clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip
create mode 100644
clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3283510c6aac7..04a13e3385d1f6 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const
llvm::Triple ,
}
case llvm::Triple::spirv64: {
if (os != llvm::Triple::UnknownOS ||
-Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
+ if (os == llvm::Triple::OSType::AMDHSA)
+return std::make_unique(Triple, Opts);
+
return nullptr;
+}
return std::make_unique(Triple, Opts);
}
case llvm::Triple::wasm32:
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index dc920177d3a910..d7d232ac9484f8 100644
---
[clang] [clang][SPIR-V] Set AS for the SPIR-V logical triple (PR #88939)
https://github.com/AlexVlx approved this pull request. LGTM, please have a peek at the comment if possible. https://github.com/llvm/llvm-project/pull/88939 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][SPIR-V] Set AS for the SPIR-V logical triple (PR #88939)
AlexVlx wrote: a) Thanks!; b) apologies for the noise; c) this was actually done on purpose, I actively eschewed changing Logical SPIRV because it wasn't actually clear to me if in the long run it'd have the same AS map / would use numerical 1 for globals. If Logical SPIRV is going to go with numerical 1 for globals, LGTM (perhaps it's worth reflecting that in [AutoUpgrade.cpp](https://github.com/llvm/llvm-project/blob/75054525ae58f26c86e418382164540760871186/llvm/lib/IR/AutoUpgrade.cpp#L5346) & associated tests, wherein the predicate guards autoupgrades from occuring on Logical SPIRV)! As a sidenote, as far as I can tell, this flared up because in LLVM's [SPIRV TargetMachine](https://github.com/llvm/llvm-project/blob/75054525ae58f26c86e418382164540760871186/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp#L56) there's no segregation between Logical & Physical SPIRV. Would it be worthwhile to add that? https://github.com/llvm/llvm-project/pull/88939 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/8] Start migrating away from the embedded assumption that
the default AS **must** be 0.
---
clang/lib/CodeGen/CGExprCXX.cpp | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 10 ++
clang/lib/CodeGen/CodeGenTypeCache.h | 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 2adbef6d55122c..b9c920a81d79c9 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -,7 +,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
LangAS GlobAS = CGM.GetGlobalVarAddressSpace(nullptr);
auto MaybeASCast = [=](auto &) {
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 8ceecff28cbc63..7dd14d32aa2d03 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -364,7 +364,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
IntTy = llvm::IntegerType::get(LLVMContext, C.getTargetInfo().getIntWidth());
IntPtrTy = llvm::IntegerType::get(LLVMContext,
C.getTargetInfo().getMaxPointerWidth());
- Int8PtrTy = llvm::PointerType::get(LLVMContext, 0);
+ Int8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetInfo().getTargetAddressSpace(LangAS::Default));
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
@@ -4512,9 +4513,10 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction(
IsIncompleteFunction = true;
}
- llvm::Function *F =
- llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, ());
+ llvm::Function *F = llvm::Function::Create(
+ FTy, llvm::Function::ExternalLinkage,
+ getDataLayout().getProgramAddressSpace(),
+ Entry ? StringRef() : MangledName, ());
// Store the declaration associated with this function so it is potentially
// updated by further declarations or definitions and emitted at the end.
diff --git a/clang/lib/CodeGen/CodeGenTypeCache.h
b/clang/lib/CodeGen/CodeGenTypeCache.h
index 083d69214fb3c2..e273ebe3b060f2 100644
--- a/clang/lib/CodeGen/CodeGenTypeCache.h
+++ b/clang/lib/CodeGen/CodeGenTypeCache.h
@@ -51,7 +51,7 @@ struct CodeGenTypeCache {
llvm::IntegerType *PtrDiffTy;
};
- /// void*, void** in address space 0
+ /// void*, void** in the target's default address space (often 0)
union {
llvm::PointerType *UnqualPtrTy;
llvm::PointerType *VoidPtrTy;
>From 74ae6f52a5f84f8fc92135df3ff93a4a89b914ed Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 25 Mar 2024 10:55:22 +0200
Subject: [PATCH 2/8] Make querying the Global AS more robust, add 1 new test
(WiP).
---
clang/lib/CodeGen/CodeGenModule.cpp | 10 ---
clang/lib/CodeGen/ItaniumCXXABI.cpp | 4 ++-
...x11-with-nonzero-default-address-space.cpp | 29 +++
3 files changed, 38 insertions(+), 5 deletions(-)
create mode 100644
clang/test/CodeGenCXX/typeid-cxx11-with-nonzero-default-address-space.cpp
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 63d54f9b1c0b60..39ccd40bf1adbb 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -371,8 +371,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
- GlobalsInt8PtrTy =
- llvm::PointerType::get(LLVMContext, DL.getDefaultGlobalsAddressSpace());
+ GlobalsInt8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetAddressSpace(GetGlobalVarAddressSpace(nullptr)));
ConstGlobalsPtrTy = llvm::PointerType::get(
LLVMContext, C.getTargetAddressSpace(GetGlobalConstantAddressSpace()));
ASTAllocaAddressSpace = getTargetCodeGenInfo().getASTAllocaAddressSpace();
@@ -5018,7 +5018,9 @@ llvm::GlobalVariable
*CodeGenModule::CreateOrReplaceCXXRuntimeVariable(
// Create a new variable.
GV = new llvm::GlobalVariable(getModule(), Ty, /*isConstant=*/true,
-Linkage, nullptr, Name);
+Linkage, nullptr, Name, nullptr,
+llvm::GlobalValue::NotThreadLocal,
+GlobalsInt8PtrTy->getAddressSpace());
if (OldGV) {
// Replace occurrences of the old variable if needed.
@@ -5133,7 +5135,7 @@ LangAS
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
@@ -3581,8 +3582,10 @@ ConstantAddress CodeGenModule::GetAddrOfTemplateParamObject( isExternallyVisible(TPO->getLinkageAndVisibility().getLinkage()) ? llvm::GlobalValue::LinkOnceODRLinkage : llvm::GlobalValue::InternalLinkage; - auto *GV = new llvm::GlobalVariable(getModule(), Init->getType(), - /*isConstant=*/true, Linkage, Init, Name); + auto *GV = new llvm::GlobalVariable( + getModule(), Init->getType(), + /*isConstant=*/true, Linkage, Init, Name, nullptr, + llvm::GlobalValue::NotThreadLocal, GlobalsInt8PtrTy->getAddressSpace()); AlexVlx wrote: This has been merged, so I'm going to mark this as done. Thank you. https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/8] Start migrating away from the embedded assumption that
the default AS **must** be 0.
---
clang/lib/CodeGen/CGExprCXX.cpp | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 10 ++
clang/lib/CodeGen/CodeGenTypeCache.h | 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 2adbef6d55122c..b9c920a81d79c9 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -,7 +,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
LangAS GlobAS = CGM.GetGlobalVarAddressSpace(nullptr);
auto MaybeASCast = [=](auto &) {
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 8ceecff28cbc63..7dd14d32aa2d03 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -364,7 +364,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
IntTy = llvm::IntegerType::get(LLVMContext, C.getTargetInfo().getIntWidth());
IntPtrTy = llvm::IntegerType::get(LLVMContext,
C.getTargetInfo().getMaxPointerWidth());
- Int8PtrTy = llvm::PointerType::get(LLVMContext, 0);
+ Int8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetInfo().getTargetAddressSpace(LangAS::Default));
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
@@ -4512,9 +4513,10 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction(
IsIncompleteFunction = true;
}
- llvm::Function *F =
- llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, ());
+ llvm::Function *F = llvm::Function::Create(
+ FTy, llvm::Function::ExternalLinkage,
+ getDataLayout().getProgramAddressSpace(),
+ Entry ? StringRef() : MangledName, ());
// Store the declaration associated with this function so it is potentially
// updated by further declarations or definitions and emitted at the end.
diff --git a/clang/lib/CodeGen/CodeGenTypeCache.h
b/clang/lib/CodeGen/CodeGenTypeCache.h
index 083d69214fb3c2..e273ebe3b060f2 100644
--- a/clang/lib/CodeGen/CodeGenTypeCache.h
+++ b/clang/lib/CodeGen/CodeGenTypeCache.h
@@ -51,7 +51,7 @@ struct CodeGenTypeCache {
llvm::IntegerType *PtrDiffTy;
};
- /// void*, void** in address space 0
+ /// void*, void** in the target's default address space (often 0)
union {
llvm::PointerType *UnqualPtrTy;
llvm::PointerType *VoidPtrTy;
>From 74ae6f52a5f84f8fc92135df3ff93a4a89b914ed Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 25 Mar 2024 10:55:22 +0200
Subject: [PATCH 2/8] Make querying the Global AS more robust, add 1 new test
(WiP).
---
clang/lib/CodeGen/CodeGenModule.cpp | 10 ---
clang/lib/CodeGen/ItaniumCXXABI.cpp | 4 ++-
...x11-with-nonzero-default-address-space.cpp | 29 +++
3 files changed, 38 insertions(+), 5 deletions(-)
create mode 100644
clang/test/CodeGenCXX/typeid-cxx11-with-nonzero-default-address-space.cpp
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 63d54f9b1c0b60..39ccd40bf1adbb 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -371,8 +371,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
- GlobalsInt8PtrTy =
- llvm::PointerType::get(LLVMContext, DL.getDefaultGlobalsAddressSpace());
+ GlobalsInt8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetAddressSpace(GetGlobalVarAddressSpace(nullptr)));
ConstGlobalsPtrTy = llvm::PointerType::get(
LLVMContext, C.getTargetAddressSpace(GetGlobalConstantAddressSpace()));
ASTAllocaAddressSpace = getTargetCodeGenInfo().getASTAllocaAddressSpace();
@@ -5018,7 +5018,9 @@ llvm::GlobalVariable
*CodeGenModule::CreateOrReplaceCXXRuntimeVariable(
// Create a new variable.
GV = new llvm::GlobalVariable(getModule(), Ty, /*isConstant=*/true,
-Linkage, nullptr, Name);
+Linkage, nullptr, Name, nullptr,
+llvm::GlobalValue::NotThreadLocal,
+GlobalsInt8PtrTy->getAddressSpace());
if (OldGV) {
// Replace occurrences of the old variable if needed.
@@ -5133,7 +5135,7 @@ LangAS
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/7] Start migrating away from the embedded assumption that
the default AS **must** be 0.
---
clang/lib/CodeGen/CGExprCXX.cpp | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 10 ++
clang/lib/CodeGen/CodeGenTypeCache.h | 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 2adbef6d55122c..b9c920a81d79c9 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -,7 +,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
LangAS GlobAS = CGM.GetGlobalVarAddressSpace(nullptr);
auto MaybeASCast = [=](auto &) {
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 8ceecff28cbc63..7dd14d32aa2d03 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -364,7 +364,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
IntTy = llvm::IntegerType::get(LLVMContext, C.getTargetInfo().getIntWidth());
IntPtrTy = llvm::IntegerType::get(LLVMContext,
C.getTargetInfo().getMaxPointerWidth());
- Int8PtrTy = llvm::PointerType::get(LLVMContext, 0);
+ Int8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetInfo().getTargetAddressSpace(LangAS::Default));
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
@@ -4512,9 +4513,10 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction(
IsIncompleteFunction = true;
}
- llvm::Function *F =
- llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, ());
+ llvm::Function *F = llvm::Function::Create(
+ FTy, llvm::Function::ExternalLinkage,
+ getDataLayout().getProgramAddressSpace(),
+ Entry ? StringRef() : MangledName, ());
// Store the declaration associated with this function so it is potentially
// updated by further declarations or definitions and emitted at the end.
diff --git a/clang/lib/CodeGen/CodeGenTypeCache.h
b/clang/lib/CodeGen/CodeGenTypeCache.h
index 083d69214fb3c2..e273ebe3b060f2 100644
--- a/clang/lib/CodeGen/CodeGenTypeCache.h
+++ b/clang/lib/CodeGen/CodeGenTypeCache.h
@@ -51,7 +51,7 @@ struct CodeGenTypeCache {
llvm::IntegerType *PtrDiffTy;
};
- /// void*, void** in address space 0
+ /// void*, void** in the target's default address space (often 0)
union {
llvm::PointerType *UnqualPtrTy;
llvm::PointerType *VoidPtrTy;
>From 74ae6f52a5f84f8fc92135df3ff93a4a89b914ed Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 25 Mar 2024 10:55:22 +0200
Subject: [PATCH 2/7] Make querying the Global AS more robust, add 1 new test
(WiP).
---
clang/lib/CodeGen/CodeGenModule.cpp | 10 ---
clang/lib/CodeGen/ItaniumCXXABI.cpp | 4 ++-
...x11-with-nonzero-default-address-space.cpp | 29 +++
3 files changed, 38 insertions(+), 5 deletions(-)
create mode 100644
clang/test/CodeGenCXX/typeid-cxx11-with-nonzero-default-address-space.cpp
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 63d54f9b1c0b60..39ccd40bf1adbb 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -371,8 +371,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
- GlobalsInt8PtrTy =
- llvm::PointerType::get(LLVMContext, DL.getDefaultGlobalsAddressSpace());
+ GlobalsInt8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetAddressSpace(GetGlobalVarAddressSpace(nullptr)));
ConstGlobalsPtrTy = llvm::PointerType::get(
LLVMContext, C.getTargetAddressSpace(GetGlobalConstantAddressSpace()));
ASTAllocaAddressSpace = getTargetCodeGenInfo().getASTAllocaAddressSpace();
@@ -5018,7 +5018,9 @@ llvm::GlobalVariable
*CodeGenModule::CreateOrReplaceCXXRuntimeVariable(
// Create a new variable.
GV = new llvm::GlobalVariable(getModule(), Ty, /*isConstant=*/true,
-Linkage, nullptr, Name);
+Linkage, nullptr, Name, nullptr,
+llvm::GlobalValue::NotThreadLocal,
+GlobalsInt8PtrTy->getAddressSpace());
if (OldGV) {
// Replace occurrences of the old variable if needed.
@@ -5133,7 +5135,7 @@ LangAS
[clang] [llvm] [clang][CodeGen] Add AS for Globals to SPIR & SPIRV datalayouts (PR #88455)
AlexVlx wrote: Merged, thanks everyone for the reviews! https://github.com/llvm/llvm-project/pull/88455 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][CodeGen] Add AS for Globals to SPIR & SPIRV datalayouts (PR #88455)
https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/88455 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][CodeGen] Add AS for Globals to SPIR & SPIRV datalayouts (PR #88455)
https://github.com/AlexVlx commented: > > Thanks @AlexVlx for this change. This should work fine for > > SPIRV-LLVM-Translator (and SPIR-V backend). Adding @michalpaszkowski for > > input from SPIR-V backend side. Recently, this restriction on LLVM IR input > > to our translator was docuemnted: > > https://github.com/KhronosGroup/SPIRV-LLVM-Translator/blob/main/docs/SPIRVRepresentationInLLVM.rst#global-variables > > _"A global variable resides in an address space, and the default address > > space in LLVM is zero. The SPIR-V storage class represented by the zero > > LLVM IR address spaces is Function. However, SPIR-V global variable > > declarations are OpVariable instructions whose Storage Class cannot be > > Function. This means that global variable declarations must always have an > > address space specified and that address space cannot be 0."_ So, your > > change will help to make the LLVM IR more suitable for the translator. > > One quick pointer. I did notice a similar commit for the AMDGPU backend - > https://reviews.llvm.org/D84345 Here, there are some updates to the > llvm/lib/IR/AutoUpgrade.cpp. Do we need similar changes here? > > Thanks I've added AutoUpgrade support. https://github.com/llvm/llvm-project/pull/88455 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][CodeGen] Add AS for Globals to SPIR & SPIRV datalayouts (PR #88455)
https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/88455 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][CodeGen] Add AS for Globals to SPIR & SPIRV datalayouts (PR #88455)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88455
>From 6d9e979f09802b94310017901b5b6b58bfa05c1c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Fri, 12 Apr 2024 00:21:02 +0100
Subject: [PATCH 1/3] Add AS 1 for Globals in the SPIR & SPIRV datalayout
strings.
---
clang/lib/Basic/Targets/SPIR.h | 8
clang/test/CodeGen/target-data.c | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h
index e25991e3dfe821..9a4a8b501460b6 100644
--- a/clang/lib/Basic/Targets/SPIR.h
+++ b/clang/lib/Basic/Targets/SPIR.h
@@ -259,7 +259,7 @@ class LLVM_LIBRARY_VISIBILITY SPIR32TargetInfo : public
SPIRTargetInfo {
SizeType = TargetInfo::UnsignedInt;
PtrDiffType = IntPtrType = TargetInfo::SignedInt;
resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
@@ -276,7 +276,7 @@ class LLVM_LIBRARY_VISIBILITY SPIR64TargetInfo : public
SPIRTargetInfo {
SizeType = TargetInfo::UnsignedLong;
PtrDiffType = IntPtrType = TargetInfo::SignedLong;
resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
@@ -336,7 +336,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRV32TargetInfo : public
BaseSPIRVTargetInfo {
SizeType = TargetInfo::UnsignedInt;
PtrDiffType = IntPtrType = TargetInfo::SignedInt;
resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
@@ -357,7 +357,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64TargetInfo : public
BaseSPIRVTargetInfo {
SizeType = TargetInfo::UnsignedLong;
PtrDiffType = IntPtrType = TargetInfo::SignedLong;
resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
diff --git a/clang/test/CodeGen/target-data.c b/clang/test/CodeGen/target-data.c
index acff367d50eb91..c184f314f68f80 100644
--- a/clang/test/CodeGen/target-data.c
+++ b/clang/test/CodeGen/target-data.c
@@ -251,11 +251,11 @@
// RUN: %clang_cc1 -triple spir-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SPIR
-// SPIR: target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+// SPIR: target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
// RUN: %clang_cc1 -triple spir64-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SPIR64
-// SPIR64: target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+// SPIR64: target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
// RUN: %clang_cc1 -triple bpfel -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=BPFEL
>From cd2d855619372143d7ec33ea4d1330c0c0e8892d Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 15 Apr 2024 21:33:05 +0100
Subject: [PATCH 2/3] Handle the LLVM side of the SPIRV target.
---
llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
index fbf64f2b1dfb13..ae8baa3f119132 100644
--- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
@@ -55,9 +55,9 @@ static std::string computeDataLayout(const Triple ) {
// mean anything.
if (Arch == Triple::spirv32)
return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
- "v96:128-v192:256-v256:256-v512:512-v1024:1024";
+ "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1";
return "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
- "v96:128-v192:256-v256:256-v512:512-v1024:1024";
+ "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1";
}
static Reloc::Model getEffectiveRelocModel(std::optional RM) {
>From 4becde6726c331c2dfc8cd7fbaffe0efd735f997 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 15 Apr 2024 21:34:12 +0100
Subject: [PATCH 3/3] Augment AutoUpgrade infra to handle legacy SPIR & SPIRV
datalayouts.
---
llvm/lib/IR/AutoUpgrade.cpp | 9 ---
.../Bitcode/DataLayoutUpgradeTest.cpp | 27 +++
2 files changed, 32 insertions(+), 4
[clang] [llvm] [clang][CodeGen] Add AS for Globals to SPIR & SPIRV datalayouts (PR #88455)
https://github.com/AlexVlx commented: > Please also fix llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp Done. https://github.com/llvm/llvm-project/pull/88455 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][CodeGen] Add AS for Globals to SPIR & SPIRV datalayouts (PR #88455)
https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/88455 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][CodeGen] Add AS for Globals to SPIR & SPIRV datalayouts (PR #88455)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88455
>From 6d9e979f09802b94310017901b5b6b58bfa05c1c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Fri, 12 Apr 2024 00:21:02 +0100
Subject: [PATCH 1/2] Add AS 1 for Globals in the SPIR & SPIRV datalayout
strings.
---
clang/lib/Basic/Targets/SPIR.h | 8
clang/test/CodeGen/target-data.c | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h
index e25991e3dfe821..9a4a8b501460b6 100644
--- a/clang/lib/Basic/Targets/SPIR.h
+++ b/clang/lib/Basic/Targets/SPIR.h
@@ -259,7 +259,7 @@ class LLVM_LIBRARY_VISIBILITY SPIR32TargetInfo : public
SPIRTargetInfo {
SizeType = TargetInfo::UnsignedInt;
PtrDiffType = IntPtrType = TargetInfo::SignedInt;
resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
@@ -276,7 +276,7 @@ class LLVM_LIBRARY_VISIBILITY SPIR64TargetInfo : public
SPIRTargetInfo {
SizeType = TargetInfo::UnsignedLong;
PtrDiffType = IntPtrType = TargetInfo::SignedLong;
resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
@@ -336,7 +336,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRV32TargetInfo : public
BaseSPIRVTargetInfo {
SizeType = TargetInfo::UnsignedInt;
PtrDiffType = IntPtrType = TargetInfo::SignedInt;
resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
@@ -357,7 +357,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64TargetInfo : public
BaseSPIRVTargetInfo {
SizeType = TargetInfo::UnsignedLong;
PtrDiffType = IntPtrType = TargetInfo::SignedLong;
resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
diff --git a/clang/test/CodeGen/target-data.c b/clang/test/CodeGen/target-data.c
index acff367d50eb91..c184f314f68f80 100644
--- a/clang/test/CodeGen/target-data.c
+++ b/clang/test/CodeGen/target-data.c
@@ -251,11 +251,11 @@
// RUN: %clang_cc1 -triple spir-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SPIR
-// SPIR: target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+// SPIR: target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
// RUN: %clang_cc1 -triple spir64-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SPIR64
-// SPIR64: target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+// SPIR64: target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
// RUN: %clang_cc1 -triple bpfel -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=BPFEL
>From cd2d855619372143d7ec33ea4d1330c0c0e8892d Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 15 Apr 2024 21:33:05 +0100
Subject: [PATCH 2/2] Handle the LLVM side of the SPIRV target.
---
llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
index fbf64f2b1dfb13..ae8baa3f119132 100644
--- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
@@ -55,9 +55,9 @@ static std::string computeDataLayout(const Triple ) {
// mean anything.
if (Arch == Triple::spirv32)
return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
- "v96:128-v192:256-v256:256-v512:512-v1024:1024";
+ "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1";
return "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
- "v96:128-v192:256-v256:256-v512:512-v1024:1024";
+ "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1";
}
static Reloc::Model getEffectiveRelocModel(std::optional RM) {
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[clang] [clang][CodeGen] Add AS for Globals to SPIR & SPIRV datalayouts (PR #88455)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88455
>From 6d9e979f09802b94310017901b5b6b58bfa05c1c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Fri, 12 Apr 2024 00:21:02 +0100
Subject: [PATCH] Add AS 1 for Globals in the SPIR & SPIRV datalayout strings.
---
clang/lib/Basic/Targets/SPIR.h | 8
clang/test/CodeGen/target-data.c | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h
index e25991e3dfe821..9a4a8b501460b6 100644
--- a/clang/lib/Basic/Targets/SPIR.h
+++ b/clang/lib/Basic/Targets/SPIR.h
@@ -259,7 +259,7 @@ class LLVM_LIBRARY_VISIBILITY SPIR32TargetInfo : public
SPIRTargetInfo {
SizeType = TargetInfo::UnsignedInt;
PtrDiffType = IntPtrType = TargetInfo::SignedInt;
resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
@@ -276,7 +276,7 @@ class LLVM_LIBRARY_VISIBILITY SPIR64TargetInfo : public
SPIRTargetInfo {
SizeType = TargetInfo::UnsignedLong;
PtrDiffType = IntPtrType = TargetInfo::SignedLong;
resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
@@ -336,7 +336,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRV32TargetInfo : public
BaseSPIRVTargetInfo {
SizeType = TargetInfo::UnsignedInt;
PtrDiffType = IntPtrType = TargetInfo::SignedInt;
resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
@@ -357,7 +357,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64TargetInfo : public
BaseSPIRVTargetInfo {
SizeType = TargetInfo::UnsignedLong;
PtrDiffType = IntPtrType = TargetInfo::SignedLong;
resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
diff --git a/clang/test/CodeGen/target-data.c b/clang/test/CodeGen/target-data.c
index acff367d50eb91..c184f314f68f80 100644
--- a/clang/test/CodeGen/target-data.c
+++ b/clang/test/CodeGen/target-data.c
@@ -251,11 +251,11 @@
// RUN: %clang_cc1 -triple spir-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SPIR
-// SPIR: target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+// SPIR: target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
// RUN: %clang_cc1 -triple spir64-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SPIR64
-// SPIR64: target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+// SPIR64: target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
// RUN: %clang_cc1 -triple bpfel -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=BPFEL
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[clang] [clang][CodeGen] Add AS for Globals to SPIR & SPIRV datalayouts (PR #88455)
AlexVlx wrote: > Thanks @AlexVlx for this change. This should work fine for > SPIRV-LLVM-Translator (and SPIR-V backend). Adding @michalpaszkowski for > input from SPIR-V backend side. Recently, this restriction on LLVM IR input > to our translator was docuemnted: > https://github.com/KhronosGroup/SPIRV-LLVM-Translator/blob/main/docs/SPIRVRepresentationInLLVM.rst#global-variables > _"A global variable resides in an address space, and the default address > space in LLVM is zero. The SPIR-V storage class represented by the zero LLVM > IR address spaces is Function. However, SPIR-V global variable declarations > are OpVariable instructions whose Storage Class cannot be Function. This > means that global variable declarations must always have an address space > specified and that address space cannot be 0."_ So, your change will help to > make the LLVM IR more suitable for the translator. > > One quick pointer. I did notice a similar commit for the AMDGPU backend - > https://reviews.llvm.org/D84345 Here, there are some updates to the > llvm/lib/IR/AutoUpgrade.cpp. Do we need similar changes here? > > Thanks Thanks for the feedback, and great call on the AutoUpgrade part, I had not considered that at all; I believe we can just re-use the AMDGPU approach, and just adapt the predicate, but I'll give it a think and then update this PR accordingly. https://github.com/llvm/llvm-project/pull/88455 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
@@ -3581,8 +3582,10 @@ ConstantAddress CodeGenModule::GetAddrOfTemplateParamObject( isExternallyVisible(TPO->getLinkageAndVisibility().getLinkage()) ? llvm::GlobalValue::LinkOnceODRLinkage : llvm::GlobalValue::InternalLinkage; - auto *GV = new llvm::GlobalVariable(getModule(), Init->getType(), - /*isConstant=*/true, Linkage, Init, Name); + auto *GV = new llvm::GlobalVariable( + getModule(), Init->getType(), + /*isConstant=*/true, Linkage, Init, Name, nullptr, + llvm::GlobalValue::NotThreadLocal, GlobalsInt8PtrTy->getAddressSpace()); AlexVlx wrote: I've opened #88455 to fix SPIR & SPIRV, which'll allow simplifying this one in the direction you have indicated. https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][CodeGen] Add AS for Globals to SPIR & SPIRV datalayouts (PR #88455)
AlexVlx wrote: > The change seems reasonable. > > > CodeGen/LLVM will default to AS0 in this case, which produces Globals that > > end up in the private address space for e.g. OCL, HIPSPV or SYCL. > > Can we add a test checking LLVM address space for globals emitted from > OCL/HIPSPV/SYCL, please? It's surprising that we need to modify only a > datalayout string check. I can add another one here, but there's a bunch of them coming in #88182, which roundabout motivated this change. I'll emphasise that this is only a problem for things such as implicitly generated globals (e.g. VTables or typeinfo for classes etc.), so it's just a subset of all globals that are impacted (there are already some tests covering direct usage AFAICS). https://github.com/llvm/llvm-project/pull/88455 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][CodeGen] Add AS for Globals to SPIR & SPIRV datalayouts (PR #88455)
https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/88455
Currently neither the SPIR nor the SPIRV targets specify the AS for globals in
their datalayout strings. This is problematic because CodeGen/LLVM will default
to AS0 in this case, which produces Globals that end up in the private address
space for e.g. OCL, HIPSPV or SYCL. This patch addresses it by completing the
datalayout string.
>From 6d9e979f09802b94310017901b5b6b58bfa05c1c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Fri, 12 Apr 2024 00:21:02 +0100
Subject: [PATCH] Add AS 1 for Globals in the SPIR & SPIRV datalayout strings.
---
clang/lib/Basic/Targets/SPIR.h | 8
clang/test/CodeGen/target-data.c | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h
index e25991e3dfe821..9a4a8b501460b6 100644
--- a/clang/lib/Basic/Targets/SPIR.h
+++ b/clang/lib/Basic/Targets/SPIR.h
@@ -259,7 +259,7 @@ class LLVM_LIBRARY_VISIBILITY SPIR32TargetInfo : public
SPIRTargetInfo {
SizeType = TargetInfo::UnsignedInt;
PtrDiffType = IntPtrType = TargetInfo::SignedInt;
resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
@@ -276,7 +276,7 @@ class LLVM_LIBRARY_VISIBILITY SPIR64TargetInfo : public
SPIRTargetInfo {
SizeType = TargetInfo::UnsignedLong;
PtrDiffType = IntPtrType = TargetInfo::SignedLong;
resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
@@ -336,7 +336,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRV32TargetInfo : public
BaseSPIRVTargetInfo {
SizeType = TargetInfo::UnsignedInt;
PtrDiffType = IntPtrType = TargetInfo::SignedInt;
resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
@@ -357,7 +357,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64TargetInfo : public
BaseSPIRVTargetInfo {
SizeType = TargetInfo::UnsignedLong;
PtrDiffType = IntPtrType = TargetInfo::SignedLong;
resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
-"v96:128-v192:256-v256:256-v512:512-v1024:1024");
+"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1");
}
void getTargetDefines(const LangOptions ,
diff --git a/clang/test/CodeGen/target-data.c b/clang/test/CodeGen/target-data.c
index acff367d50eb91..c184f314f68f80 100644
--- a/clang/test/CodeGen/target-data.c
+++ b/clang/test/CodeGen/target-data.c
@@ -251,11 +251,11 @@
// RUN: %clang_cc1 -triple spir-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SPIR
-// SPIR: target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+// SPIR: target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
// RUN: %clang_cc1 -triple spir64-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SPIR64
-// SPIR64: target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+// SPIR64: target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
// RUN: %clang_cc1 -triple bpfel -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=BPFEL
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[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
@@ -3581,8 +3582,10 @@ ConstantAddress CodeGenModule::GetAddrOfTemplateParamObject( isExternallyVisible(TPO->getLinkageAndVisibility().getLinkage()) ? llvm::GlobalValue::LinkOnceODRLinkage : llvm::GlobalValue::InternalLinkage; - auto *GV = new llvm::GlobalVariable(getModule(), Init->getType(), - /*isConstant=*/true, Linkage, Init, Name); + auto *GV = new llvm::GlobalVariable( + getModule(), Init->getType(), + /*isConstant=*/true, Linkage, Init, Name, nullptr, + llvm::GlobalValue::NotThreadLocal, GlobalsInt8PtrTy->getAddressSpace()); AlexVlx wrote: At the same time, it's not terribly costly (except for lines of code), and, unfortunately, there might be quite a few "broken" datalayouts (NVPTX is in the same boat, as is DirectX). I'm not entirely convinced the breakage is not an intentional design choice for pseudo/meta/abstract targets (abusing nomenclature, apologies). I'd submit that this (the changes/CodeGen) is still in Clang, which would still fall under the "the FE/language has to deal with ASes having special properties, LLVM shouldn't care", and it is an artifact of composing AS aware languages (OCL/CUDA/HIP etc.) with said abstract targets. https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
@@ -2216,7 +2216,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
AlexVlx wrote:
It should but sadly it cannot, see our historical conversation here:
. I've not got around to working on your
suggestion there about supporting declaring a default AS for a class, so we
have to keep things like so for now.
https://github.com/llvm/llvm-project/pull/88182
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[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
@@ -4551,6 +4554,7 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction( llvm::Function *F = llvm::Function::Create(FTy, llvm::Function::ExternalLinkage, + getDataLayout().getProgramAddressSpace(), AlexVlx wrote: Whoops, that's a mistake, apologies. Fixed. https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/7] Start migrating away from the embedded assumption that
the default AS **must** be 0.
---
clang/lib/CodeGen/CGExprCXX.cpp | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 10 ++
clang/lib/CodeGen/CodeGenTypeCache.h | 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 2adbef6d55122c..b9c920a81d79c9 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -,7 +,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
LangAS GlobAS = CGM.GetGlobalVarAddressSpace(nullptr);
auto MaybeASCast = [=](auto &) {
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 8ceecff28cbc63..7dd14d32aa2d03 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -364,7 +364,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
IntTy = llvm::IntegerType::get(LLVMContext, C.getTargetInfo().getIntWidth());
IntPtrTy = llvm::IntegerType::get(LLVMContext,
C.getTargetInfo().getMaxPointerWidth());
- Int8PtrTy = llvm::PointerType::get(LLVMContext, 0);
+ Int8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetInfo().getTargetAddressSpace(LangAS::Default));
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
@@ -4512,9 +4513,10 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction(
IsIncompleteFunction = true;
}
- llvm::Function *F =
- llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, ());
+ llvm::Function *F = llvm::Function::Create(
+ FTy, llvm::Function::ExternalLinkage,
+ getDataLayout().getProgramAddressSpace(),
+ Entry ? StringRef() : MangledName, ());
// Store the declaration associated with this function so it is potentially
// updated by further declarations or definitions and emitted at the end.
diff --git a/clang/lib/CodeGen/CodeGenTypeCache.h
b/clang/lib/CodeGen/CodeGenTypeCache.h
index 083d69214fb3c2..e273ebe3b060f2 100644
--- a/clang/lib/CodeGen/CodeGenTypeCache.h
+++ b/clang/lib/CodeGen/CodeGenTypeCache.h
@@ -51,7 +51,7 @@ struct CodeGenTypeCache {
llvm::IntegerType *PtrDiffTy;
};
- /// void*, void** in address space 0
+ /// void*, void** in the target's default address space (often 0)
union {
llvm::PointerType *UnqualPtrTy;
llvm::PointerType *VoidPtrTy;
>From 74ae6f52a5f84f8fc92135df3ff93a4a89b914ed Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 25 Mar 2024 10:55:22 +0200
Subject: [PATCH 2/7] Make querying the Global AS more robust, add 1 new test
(WiP).
---
clang/lib/CodeGen/CodeGenModule.cpp | 10 ---
clang/lib/CodeGen/ItaniumCXXABI.cpp | 4 ++-
...x11-with-nonzero-default-address-space.cpp | 29 +++
3 files changed, 38 insertions(+), 5 deletions(-)
create mode 100644
clang/test/CodeGenCXX/typeid-cxx11-with-nonzero-default-address-space.cpp
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 63d54f9b1c0b60..39ccd40bf1adbb 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -371,8 +371,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
- GlobalsInt8PtrTy =
- llvm::PointerType::get(LLVMContext, DL.getDefaultGlobalsAddressSpace());
+ GlobalsInt8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetAddressSpace(GetGlobalVarAddressSpace(nullptr)));
ConstGlobalsPtrTy = llvm::PointerType::get(
LLVMContext, C.getTargetAddressSpace(GetGlobalConstantAddressSpace()));
ASTAllocaAddressSpace = getTargetCodeGenInfo().getASTAllocaAddressSpace();
@@ -5018,7 +5018,9 @@ llvm::GlobalVariable
*CodeGenModule::CreateOrReplaceCXXRuntimeVariable(
// Create a new variable.
GV = new llvm::GlobalVariable(getModule(), Ty, /*isConstant=*/true,
-Linkage, nullptr, Name);
+Linkage, nullptr, Name, nullptr,
+llvm::GlobalValue::NotThreadLocal,
+GlobalsInt8PtrTy->getAddressSpace());
if (OldGV) {
// Replace occurrences of the old variable if needed.
@@ -5133,7 +5135,7 @@ LangAS
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
AlexVlx wrote:
> > I'm not quite sure how to parse this comment, could you explain what you
> > have in mind here? The problem is precisely that the FE assumes 0 is fine /
> > picks it by default, which ends up into dangerzones when e.g. a target
> > happened to use 0 to point to private (stack). I feel as if I'm missing the
> > core of your comment though, so apologies in advance.
>
> I'm just saying that I don't think it makes any sense to add a concept of a
> default AS to LLVM. The "default" AS is a frontend-level concept about how to
> interpret source-level types , not an LLVM-level concept. LLVM would only
> need a default AS if it were inventing a memory allocation/operation from
> whole cloth, which is generally not something LLVM should be doing except in
> local memory; the only legitimate counter-example I can think of would be
> something like materializing a constant into constant global memory, in which
> case LLVM needs to assign the new constant an AS.
Thinking about this a bit more, is it not the case that today, we do have a _de
facto_ default AS in LLVM, if only by virtue of the fact that an unqualified
ptr ends up as a ptr to AS 0; unqualified ptrs are used all over the place /
the FE is pretty liberal in their employ? So, it's possible that a large part
of this pain is that we say stuff like the below:
```cpp
/// void*, void** in address space 0
union {
llvm::PointerType *UnqualPtrTy;
```
https://github.com/llvm/llvm-project/pull/88182
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[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
AlexVlx wrote: > > I'm not quite sure how to parse this comment, could you explain what you > > have in mind here? The problem is precisely that the FE assumes 0 is fine / > > picks it by default, which ends up into dangerzones when e.g. a target > > happened to use 0 to point to private (stack). I feel as if I'm missing the > > core of your comment though, so apologies in advance. > > I'm just saying that I don't think it makes any sense to add a concept of a > default AS to LLVM. The "default" AS is a frontend concept, not a middle-end > / back-end concept. LLVM would only need a default AS if it were inventing a > memory allocation/operation from whole cloth, which is generally not > something LLVM should be doing except in local memory; the only legitimate > counter-example I can think of would be something like materializing a > constant into constant global memory, in which case LLVM needs to assign the > new constant an AS. Ah, ok, I was misreading what you said. I agree; however, I believe that it might make sense to enforce / enshrine that `0` has to be generic i.e. targets shouldn't use `0` creatively, precisely so as to make it a safe default for FEs. Otherwise, if a target uses `0` to refer to a peculiar memory space (say, addresses are of a different size, there are some very odd allocation constraints etc.), the sort of issues that motivated this patch, emerge. I don't know how feasible this is / how much retroactive churn it'd cause. https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx commented: > > querying a modules global AS from the target, rather than from the data > > layout (some DL's are incomplete, e.g. SPIRV's) That is a bug in those DataLayouts Do we spell out the requirement somewhere? I am only asking because, for example, [neither SPIR nor SPIRV have a complete DL string](https://github.com/llvm/llvm-project/blob/main/clang/lib/Basic/Targets/SPIR.h). https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx commented: > It's very uncommon for LLVM to need to come up with an address space on its > own, as opposed to just propagating the original address space of some memory > / operation as chosen by the frontend. LLVM occasionally creates new storage > allocations, but usually they're (non-escaping) `alloca`s and therefore have > to be in the `alloca` AS. The only situation I can think of where LLVM might > legitimately have to come with an address space is when LLVM decides to > introduce new global constants. (I can't think of any transformation that > would introduce a *non-constant* global.) So if you add a default AS to > `DataLayout`, please focus on that specifically and call it something like a > "preferred constant address space" rather than some sort of default AS. The > default AS for pointer types and so on is really a frontend issue that's none > of LLVM's business to know about. I'm not quite sure how to parse this comment, could you explain what you have in mind here? The problem is precisely that the FE assumes 0 is fine / picks it by default, which ends up into dangerzones when e.g. a target happened to use 0 to point to private (stack). I feel as if I'm missing the core of your comment though, so apologies in advance. https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx commented: > Why can't we just declare that the "generic" address-space must always be 0? > The specific numbers we use for address-spaces are completely arbitrary > anyway. If we were to do this, some targets would need to change to accomodate it; it would also probably break folks that are making naughty assumptions about the numbers actually meaning special things on this or that target - we can reasonably argue that's not quite kosher, but it'd cause some friction, I suspect. Personally I'd prefer that / think it'd have been really nice to legislate it as such back in the dawn of time. I will note that even if we do that we'll probably needs some bits from this patch (e.g. using the explicit `GlobalVariable` ctor or, alternatively, changing the default value for the AS used there). https://github.com/llvm/llvm-project/pull/88182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/6] Start migrating away from the embedded assumption that
the default AS **must** be 0.
---
clang/lib/CodeGen/CGExprCXX.cpp | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 10 ++
clang/lib/CodeGen/CodeGenTypeCache.h | 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 2adbef6d55122c..b9c920a81d79c9 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -,7 +,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
LangAS GlobAS = CGM.GetGlobalVarAddressSpace(nullptr);
auto MaybeASCast = [=](auto &) {
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 8ceecff28cbc63..7dd14d32aa2d03 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -364,7 +364,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
IntTy = llvm::IntegerType::get(LLVMContext, C.getTargetInfo().getIntWidth());
IntPtrTy = llvm::IntegerType::get(LLVMContext,
C.getTargetInfo().getMaxPointerWidth());
- Int8PtrTy = llvm::PointerType::get(LLVMContext, 0);
+ Int8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetInfo().getTargetAddressSpace(LangAS::Default));
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
@@ -4512,9 +4513,10 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction(
IsIncompleteFunction = true;
}
- llvm::Function *F =
- llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, ());
+ llvm::Function *F = llvm::Function::Create(
+ FTy, llvm::Function::ExternalLinkage,
+ getDataLayout().getProgramAddressSpace(),
+ Entry ? StringRef() : MangledName, ());
// Store the declaration associated with this function so it is potentially
// updated by further declarations or definitions and emitted at the end.
diff --git a/clang/lib/CodeGen/CodeGenTypeCache.h
b/clang/lib/CodeGen/CodeGenTypeCache.h
index 083d69214fb3c2..e273ebe3b060f2 100644
--- a/clang/lib/CodeGen/CodeGenTypeCache.h
+++ b/clang/lib/CodeGen/CodeGenTypeCache.h
@@ -51,7 +51,7 @@ struct CodeGenTypeCache {
llvm::IntegerType *PtrDiffTy;
};
- /// void*, void** in address space 0
+ /// void*, void** in the target's default address space (often 0)
union {
llvm::PointerType *UnqualPtrTy;
llvm::PointerType *VoidPtrTy;
>From 74ae6f52a5f84f8fc92135df3ff93a4a89b914ed Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 25 Mar 2024 10:55:22 +0200
Subject: [PATCH 2/6] Make querying the Global AS more robust, add 1 new test
(WiP).
---
clang/lib/CodeGen/CodeGenModule.cpp | 10 ---
clang/lib/CodeGen/ItaniumCXXABI.cpp | 4 ++-
...x11-with-nonzero-default-address-space.cpp | 29 +++
3 files changed, 38 insertions(+), 5 deletions(-)
create mode 100644
clang/test/CodeGenCXX/typeid-cxx11-with-nonzero-default-address-space.cpp
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 63d54f9b1c0b60..39ccd40bf1adbb 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -371,8 +371,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
- GlobalsInt8PtrTy =
- llvm::PointerType::get(LLVMContext, DL.getDefaultGlobalsAddressSpace());
+ GlobalsInt8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetAddressSpace(GetGlobalVarAddressSpace(nullptr)));
ConstGlobalsPtrTy = llvm::PointerType::get(
LLVMContext, C.getTargetAddressSpace(GetGlobalConstantAddressSpace()));
ASTAllocaAddressSpace = getTargetCodeGenInfo().getASTAllocaAddressSpace();
@@ -5018,7 +5018,9 @@ llvm::GlobalVariable
*CodeGenModule::CreateOrReplaceCXXRuntimeVariable(
// Create a new variable.
GV = new llvm::GlobalVariable(getModule(), Ty, /*isConstant=*/true,
-Linkage, nullptr, Name);
+Linkage, nullptr, Name, nullptr,
+llvm::GlobalValue::NotThreadLocal,
+GlobalsInt8PtrTy->getAddressSpace());
if (OldGV) {
// Replace occurrences of the old variable if needed.
@@ -5133,7 +5135,7 @@ LangAS
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/5] Start migrating away from the embedded assumption that
the default AS **must** be 0.
---
clang/lib/CodeGen/CGExprCXX.cpp | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 10 ++
clang/lib/CodeGen/CodeGenTypeCache.h | 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 2adbef6d55122c..b9c920a81d79c9 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -,7 +,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
LangAS GlobAS = CGM.GetGlobalVarAddressSpace(nullptr);
auto MaybeASCast = [=](auto &) {
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 8ceecff28cbc63..7dd14d32aa2d03 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -364,7 +364,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
IntTy = llvm::IntegerType::get(LLVMContext, C.getTargetInfo().getIntWidth());
IntPtrTy = llvm::IntegerType::get(LLVMContext,
C.getTargetInfo().getMaxPointerWidth());
- Int8PtrTy = llvm::PointerType::get(LLVMContext, 0);
+ Int8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetInfo().getTargetAddressSpace(LangAS::Default));
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
@@ -4512,9 +4513,10 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction(
IsIncompleteFunction = true;
}
- llvm::Function *F =
- llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, ());
+ llvm::Function *F = llvm::Function::Create(
+ FTy, llvm::Function::ExternalLinkage,
+ getDataLayout().getProgramAddressSpace(),
+ Entry ? StringRef() : MangledName, ());
// Store the declaration associated with this function so it is potentially
// updated by further declarations or definitions and emitted at the end.
diff --git a/clang/lib/CodeGen/CodeGenTypeCache.h
b/clang/lib/CodeGen/CodeGenTypeCache.h
index 083d69214fb3c2..e273ebe3b060f2 100644
--- a/clang/lib/CodeGen/CodeGenTypeCache.h
+++ b/clang/lib/CodeGen/CodeGenTypeCache.h
@@ -51,7 +51,7 @@ struct CodeGenTypeCache {
llvm::IntegerType *PtrDiffTy;
};
- /// void*, void** in address space 0
+ /// void*, void** in the target's default address space (often 0)
union {
llvm::PointerType *UnqualPtrTy;
llvm::PointerType *VoidPtrTy;
>From 74ae6f52a5f84f8fc92135df3ff93a4a89b914ed Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 25 Mar 2024 10:55:22 +0200
Subject: [PATCH 2/5] Make querying the Global AS more robust, add 1 new test
(WiP).
---
clang/lib/CodeGen/CodeGenModule.cpp | 10 ---
clang/lib/CodeGen/ItaniumCXXABI.cpp | 4 ++-
...x11-with-nonzero-default-address-space.cpp | 29 +++
3 files changed, 38 insertions(+), 5 deletions(-)
create mode 100644
clang/test/CodeGenCXX/typeid-cxx11-with-nonzero-default-address-space.cpp
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 63d54f9b1c0b60..39ccd40bf1adbb 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -371,8 +371,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
- GlobalsInt8PtrTy =
- llvm::PointerType::get(LLVMContext, DL.getDefaultGlobalsAddressSpace());
+ GlobalsInt8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetAddressSpace(GetGlobalVarAddressSpace(nullptr)));
ConstGlobalsPtrTy = llvm::PointerType::get(
LLVMContext, C.getTargetAddressSpace(GetGlobalConstantAddressSpace()));
ASTAllocaAddressSpace = getTargetCodeGenInfo().getASTAllocaAddressSpace();
@@ -5018,7 +5018,9 @@ llvm::GlobalVariable
*CodeGenModule::CreateOrReplaceCXXRuntimeVariable(
// Create a new variable.
GV = new llvm::GlobalVariable(getModule(), Ty, /*isConstant=*/true,
-Linkage, nullptr, Name);
+Linkage, nullptr, Name, nullptr,
+llvm::GlobalValue::NotThreadLocal,
+GlobalsInt8PtrTy->getAddressSpace());
if (OldGV) {
// Replace occurrences of the old variable if needed.
@@ -5133,7 +5135,7 @@ LangAS
[clang] [Clang][CodeGen] Start migrating away from assuming the Default AS is 0 (PR #88182)
https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/88182
At the moment, Clang is rather liberal in assuming that 0 (and by extension
unqualified) is always a safe default. This does not work for targets that
actually use a different value for the default / generic AS (for example, the
SPIRV that obtains from HIPSPV or SYCL). This patch is a first step, fairly
safe step towards trying to clear things up by:
- querying a modules default AS from the target, rather than assuming it's 0
- querying a modules global AS from the target, rather than from the data
layout (some DL's are incomplete, e.g. SPIRV's)
- using the overloaded ctors for `GlobalVariable`s / `Function`s that take an
address space argument, as opposed to the defaults that assume 0.
A bunch of tests (adapted from existing ones) are added. I've opted against
adding new cases within to the existing ones sinc e some are fairly verbose
already.
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/4] Start migrating away from the embedded assumption that
the default AS **must** be 0.
---
clang/lib/CodeGen/CGExprCXX.cpp | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 10 ++
clang/lib/CodeGen/CodeGenTypeCache.h | 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 2adbef6d55122c..b9c920a81d79c9 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -,7 +,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy = Int8PtrTy;
LangAS GlobAS = CGM.GetGlobalVarAddressSpace(nullptr);
auto MaybeASCast = [=](auto &) {
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 8ceecff28cbc63..7dd14d32aa2d03 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -364,7 +364,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
IntTy = llvm::IntegerType::get(LLVMContext, C.getTargetInfo().getIntWidth());
IntPtrTy = llvm::IntegerType::get(LLVMContext,
C.getTargetInfo().getMaxPointerWidth());
- Int8PtrTy = llvm::PointerType::get(LLVMContext, 0);
+ Int8PtrTy = llvm::PointerType::get(
+ LLVMContext, C.getTargetInfo().getTargetAddressSpace(LangAS::Default));
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
@@ -4512,9 +4513,10 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction(
IsIncompleteFunction = true;
}
- llvm::Function *F =
- llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, ());
+ llvm::Function *F = llvm::Function::Create(
+ FTy, llvm::Function::ExternalLinkage,
+ getDataLayout().getProgramAddressSpace(),
+ Entry ? StringRef() : MangledName, ());
// Store the declaration associated with this function so it is potentially
// updated by further declarations or definitions and emitted at the end.
diff --git a/clang/lib/CodeGen/CodeGenTypeCache.h
b/clang/lib/CodeGen/CodeGenTypeCache.h
index 083d69214fb3c2..e273ebe3b060f2 100644
--- a/clang/lib/CodeGen/CodeGenTypeCache.h
+++ b/clang/lib/CodeGen/CodeGenTypeCache.h
@@ -51,7 +51,7 @@ struct CodeGenTypeCache {
llvm::IntegerType *PtrDiffTy;
};
- /// void*, void** in address space 0
+ /// void*, void** in the target's default address space (often 0)
union {
llvm::PointerType *UnqualPtrTy;
llvm::PointerType *VoidPtrTy;
>From 74ae6f52a5f84f8fc92135df3ff93a4a89b914ed Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 25 Mar 2024 10:55:22 +0200
Subject: [PATCH 2/4] Make querying the Global AS more robust, add 1 new test
(WiP).
---
clang/lib/CodeGen/CodeGenModule.cpp | 10 ---
clang/lib/CodeGen/ItaniumCXXABI.cpp | 4 ++-
...x11-with-nonzero-default-address-space.cpp | 29 +++
3 files changed, 38 insertions(+), 5 deletions(-)
create mode 100644
clang/test/CodeGenCXX/typeid-cxx11-with-nonzero-default-address-space.cpp
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 63d54f9b1c0b60..39ccd40bf1adbb 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -371,8 +371,8 @@ CodeGenModule::CodeGenModule(ASTContext ,
const llvm::DataLayout = M.getDataLayout();
AllocaInt8PtrTy =
llvm::PointerType::get(LLVMContext, DL.getAllocaAddrSpace());
- GlobalsInt8PtrTy =
- llvm::PointerType::get(LLVMContext, DL.getDefaultGlobalsAddressSpace());
+ GlobalsInt8PtrTy = llvm::PointerType::get(
+
[clang] [llvm] [mlir] [CodeGen][LLVM] Make the `va_list` related intrinsics generic. (PR #85460)
AlexVlx wrote: Thank you everyone for the reviews. https://github.com/llvm/llvm-project/pull/85460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [CodeGen][LLVM] Make the `va_list` related intrinsics generic. (PR #85460)
https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/85460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [CodeGen][LLVM] Make the `va_list` related intrinsics generic. (PR #85460)
AlexVlx wrote: > CI looks unhappy, mlir also seems to need updates: > > MLIR :: Target/LLVMIR/llvmir.mlir MLIR :: mlir-cpu-runner/x86-varargs.mlir Done. https://github.com/llvm/llvm-project/pull/85460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CodeGen][LLVM] Make the `va_list` related intrinsics generic. (PR #85460)
@@ -1318,16 +1318,16 @@ define void @instructions.va_arg(i8* %v, ...) {
%ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2)
- ; CHECK: call void @llvm.va_start(ptr %ap2)
+ ; CHECK: call void @llvm.va_start.p0(ptr %ap2)
va_arg i8* %ap2, i32
; CHECK: va_arg ptr %ap2, i32
-
+s
AlexVlx wrote:
Done.
https://github.com/llvm/llvm-project/pull/85460
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[clang] [llvm] [CodeGen][LLVM] Make the `va_list` related intrinsics generic. (PR #85460)
@@ -700,10 +700,13 @@ class MSBuiltin {
//===--- Variable Argument Handling Intrinsics
===//
//
-def int_vastart : DefaultAttrsIntrinsic<[], [llvm_ptr_ty], [],
"llvm.va_start">;
-def int_vacopy : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], [],
-"llvm.va_copy">;
-def int_vaend : DefaultAttrsIntrinsic<[], [llvm_ptr_ty], [], "llvm.va_end">;
+def int_vastart : DefaultAttrsIntrinsic<[],
+[llvm_anyptr_ty], [], "llvm.va_start">;
+def int_vacopy : DefaultAttrsIntrinsic<[],
+[llvm_anyptr_ty, llvm_anyptr_ty], [],
+"llvm.va_copy">;
AlexVlx wrote:
Ok, I think you and @arsenm have the right of it, I've taken Matt's suggestion.
https://github.com/llvm/llvm-project/pull/85460
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[clang] [llvm] [CodeGen][LLVM] Make the `va_list` related intrinsics generic. (PR #85460)
@@ -700,10 +700,13 @@ class MSBuiltin {
//===--- Variable Argument Handling Intrinsics
===//
//
-def int_vastart : DefaultAttrsIntrinsic<[], [llvm_ptr_ty], [],
"llvm.va_start">;
-def int_vacopy : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], [],
-"llvm.va_copy">;
-def int_vaend : DefaultAttrsIntrinsic<[], [llvm_ptr_ty], [], "llvm.va_end">;
+def int_vastart : DefaultAttrsIntrinsic<[],
+[llvm_anyptr_ty], [], "llvm.va_start">;
+def int_vacopy : DefaultAttrsIntrinsic<[],
+[llvm_anyptr_ty, llvm_anyptr_ty], [],
+"llvm.va_copy">;
AlexVlx wrote:
It does for our target, but I believe each target has freedom when it comes to
implementing the actual `va_list` underlying type (the standard regards it as
opaque), so it is probably legal to do things that do not match that. So I'd
rather follow up with some AMDGPU specific work, but leave this as general /
generic as possible.
https://github.com/llvm/llvm-project/pull/85460
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[clang] [llvm] [CodeGen][LLVM] Make the `va_list` related intrinsics generic. (PR #85460)
@@ -700,10 +700,13 @@ class MSBuiltin {
//===--- Variable Argument Handling Intrinsics
===//
//
-def int_vastart : DefaultAttrsIntrinsic<[], [llvm_ptr_ty], [],
"llvm.va_start">;
-def int_vacopy : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], [],
-"llvm.va_copy">;
-def int_vaend : DefaultAttrsIntrinsic<[], [llvm_ptr_ty], [], "llvm.va_end">;
+def int_vastart : DefaultAttrsIntrinsic<[],
+[llvm_anyptr_ty], [], "llvm.va_start">;
+def int_vacopy : DefaultAttrsIntrinsic<[],
+[llvm_anyptr_ty, llvm_anyptr_ty], [],
+"llvm.va_copy">;
AlexVlx wrote:
Hmm, I did struggle a bit with this and admit that I'm not (yet) entirely
convinced a valid (albeit hypothetical and admittedly odd) case couldn't be
constructed. Consider e.g. having a `__builtin_va_list` declared at namespace /
global scope. If a target uses an explicit, non-generic, AS, for globals, then
the copy would be to/from a pointer to generic (or pointer to private) from/to
a pointer to global. I _believe_ this should work, and making `va_copy`
mono-parameter would break it, would it not?
https://github.com/llvm/llvm-project/pull/85460
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[clang] [llvm] [CodeGen][LLVM] Make the `va_list` related intrinsics generic. (PR #85460)
@@ -1713,7 +1716,7 @@ def int_coro_subfn_addr : DefaultAttrsIntrinsic< ///===-- Other Intrinsics --===// // -// TODO: We should introduce a new memory kind fo traps (and other side effects +// TODO: We should introduce a new memory kind fo traps (and other side effects AlexVlx wrote: Done. https://github.com/llvm/llvm-project/pull/85460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CodeGen][LLVM] Make the `va_list` related intrinsics generic. (PR #85460)
@@ -0,0 +1,22 @@ +// REQUIRES: spirv-registered-target AlexVlx wrote: I was not certain and erred on the side of caution. You are correct (as far as I can tell), and have removed the requirement. Thank you for pointing it out! https://github.com/llvm/llvm-project/pull/85460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CodeGen][LLVM] Make the `va_list` related intrinsics generic. (PR #85460)
@@ -0,0 +1,22 @@
+// REQUIRES: spirv-registered-target
+// RUN: %clang_cc1 -triple spirv64-unknown-unknown -fcuda-is-device -emit-llvm
-o - %s | FileCheck %s
+struct x {
+ double b;
+ long a;
+};
+
+void testva(int n, ...) {
+ __builtin_va_list ap;
+ __builtin_va_start(ap, n);
+ struct x t = __builtin_va_arg(ap, struct x);
+ __builtin_va_list ap2;
+ __builtin_va_copy(ap2, ap);
+ int v = __builtin_va_arg(ap2, int);
+ __builtin_va_end(ap2);
+ __builtin_va_end(ap);
+}
+
+// CHECK: call void @llvm.va_start.p4(ptr addrspace(4) %ap{{.*}})
AlexVlx wrote:
Done.
https://github.com/llvm/llvm-project/pull/85460
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[clang] [llvm] [CodeGen][LLVM] Make the `va_list` related intrinsics generic. (PR #85460)
@@ -0,0 +1,22 @@
+// REQUIRES: spirv-registered-target
+// RUN: %clang_cc1 -triple spirv64-unknown-unknown -fcuda-is-device -emit-llvm
-o - %s | FileCheck %s
+struct x {
AlexVlx wrote:
Done.
https://github.com/llvm/llvm-project/pull/85460
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[clang] [lld] [llvm] [flang] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)
@@ -139,10 +139,10 @@ bool
AMDGPURemoveIncompatibleFunctions::checkFunction(Function ) {
const GCNSubtarget *ST =
static_cast(TM->getSubtargetImpl(F));
- // Check the GPU isn't generic. Generic is used for testing only
- // and we don't want this pass to interfere with it.
+ // Check the GPU isn't generic or generic-hsa. Generic is used for testing
+ // only and we don't want this pass to interfere with it.
StringRef GPUName = ST->getCPU();
- if (GPUName.empty() || GPUName.contains("generic"))
+ if (GPUName.empty() || GPUName.starts_with("generic"))
AlexVlx wrote:
Are we sure this is correct? The existing issue (as far as I can tell) is that
we never really implemented `generic`, so it'd just end up as some specific.
However, with generic targets, it appears that the pass would actually make
sense / apply / have some use?
https://github.com/llvm/llvm-project/pull/76955
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[flang] [llvm] [lld] [clang] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)
@@ -49,6 +49,11 @@ constexpr uint32_t VersionMajorV5 = 1; /// HSA metadata minor version for code object V5. constexpr uint32_t VersionMinorV5 = 2; +/// HSA metadata major version for code object V6. +constexpr uint32_t VersionMajorV6 = 1; +/// HSA metadata minor version for code object V6. +constexpr uint32_t VersionMinorV6 = 3; AlexVlx wrote: Minor nit: there's formally no HSA 1.3, as far as I recall (things stopped at 1.2). Someone looking at this might erroneously infer it exists as a foundation mandated standard (and go look up the documentation), or assume it's coming soonTM. It might be beneficial to call that out here, since it would be difficult to break the current progression / use of "HSA" metadata. https://github.com/llvm/llvm-project/pull/76955 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[lld] [clang] [flang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)
https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/76955 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [llvm] [lld] [clang] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)
https://github.com/AlexVlx approved this pull request. LGTM in general, versioning seems fine; I had a pair of very minor nits/questions, but they're not blocking concerns. Thanks! https://github.com/llvm/llvm-project/pull/76955 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [HIP][Driver] Automatically include `hipstdpar` forwarding header (PR #78915)
https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/78915 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [HIP][Driver] Automatically include `hipstdpar` forwarding header (PR #78915)
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/78915
>From 37453ff13fd7a61f2072069cf94615497c748089 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Sun, 21 Jan 2024 21:52:52 +
Subject: [PATCH 1/2] Add automated inclusion for the forwarding header
packaged with `rocThrust`.
---
clang/lib/Driver/ToolChains/AMDGPU.cpp | 25 +
clang/test/Driver/hipstdpar.c | 3 ++-
2 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp
b/clang/lib/Driver/ToolChains/AMDGPU.cpp
index 56f06fc5fccb7eb..8a88dba562c8c02 100644
--- a/clang/lib/Driver/ToolChains/AMDGPU.cpp
+++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp
@@ -545,26 +545,35 @@ void RocmInstallationDetector::AddHIPIncludeArgs(const
ArgList ,
}
const auto HandleHipStdPar = [=, , ]() {
-if (!hasHIPStdParLibrary()) {
+StringRef Inc = getIncludePath();
+auto = D.getVFS();
+
+if (!hasHIPStdParLibrary())
+ if (!HIPStdParPathArg.empty() ||
+ !FS.exists(Inc + "/thrust/system/hip/hipstdpar/hipstdpar_lib.hpp")) {
D.Diag(diag::err_drv_no_hipstdpar_lib);
return;
}
-if (!HasRocThrustLibrary &&
-!D.getVFS().exists(getIncludePath() + "/thrust")) {
+if (!HasRocThrustLibrary && !FS.exists(Inc + "/thrust")) {
D.Diag(diag::err_drv_no_hipstdpar_thrust_lib);
return;
}
-if (!HasRocPrimLibrary &&
-!D.getVFS().exists(getIncludePath() + "/rocprim")) {
+if (!HasRocPrimLibrary && !FS.exists(Inc + "/rocprim")) {
D.Diag(diag::err_drv_no_hipstdpar_prim_lib);
return;
}
-
const char *ThrustPath;
if (HasRocThrustLibrary)
ThrustPath = DriverArgs.MakeArgString(HIPRocThrustPathArg);
else
- ThrustPath = DriverArgs.MakeArgString(getIncludePath() + "/thrust");
+ ThrustPath = DriverArgs.MakeArgString(Inc + "/thrust");
+
+const char *HIPStdParPath;
+if (hasHIPStdParLibrary())
+ HIPStdParPath = DriverArgs.MakeArgString(HIPStdParPathArg);
+else
+ HIPStdParPath = DriverArgs.MakeArgString(StringRef(ThrustPath) +
+ "/system/hip/hipstdpar");
const char *PrimPath;
if (HasRocPrimLibrary)
@@ -573,7 +582,7 @@ void RocmInstallationDetector::AddHIPIncludeArgs(const
ArgList ,
PrimPath = DriverArgs.MakeArgString(getIncludePath() + "/rocprim");
CC1Args.append({"-idirafter", ThrustPath, "-idirafter", PrimPath,
-"-idirafter", DriverArgs.MakeArgString(HIPStdParPathArg),
+"-idirafter", HIPStdParPath,
"-include", "hipstdpar_lib.hpp"});
};
diff --git a/clang/test/Driver/hipstdpar.c b/clang/test/Driver/hipstdpar.c
index 69c5b177d170cd8..2f48bf6b5cf1ebd 100644
--- a/clang/test/Driver/hipstdpar.c
+++ b/clang/test/Driver/hipstdpar.c
@@ -5,7 +5,8 @@
// XFAIL: target={{.*}}-scei{{.*}}
// XFAIL: target={{.*}}-sie{{.*}}
-// RUN: not %clang -### --hipstdpar -nogpulib -nogpuinc --compile %s 2>&1 | \
+// RUN: not %clang -### --hipstdpar --hipstdpar-path=/does/not/exist -nogpulib
\
+// RUN: -nogpuinc --compile %s 2>&1 | \
// RUN: FileCheck --check-prefix=HIPSTDPAR-MISSING-LIB %s
// RUN: %clang -### --hipstdpar --hipstdpar-path=%S/Inputs/hipstdpar \
// RUN: --hipstdpar-thrust-path=%S/Inputs/hipstdpar/thrust \
>From b4ad26f6213aec78adcac302ee915420eebc4c16 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Sun, 21 Jan 2024 22:04:12 +
Subject: [PATCH 2/2] Fix formatting.
---
clang/lib/Driver/ToolChains/AMDGPU.cpp | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp
b/clang/lib/Driver/ToolChains/AMDGPU.cpp
index 8a88dba562c8c02..b3c9d5908654f6a 100644
--- a/clang/lib/Driver/ToolChains/AMDGPU.cpp
+++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp
@@ -551,9 +551,9 @@ void RocmInstallationDetector::AddHIPIncludeArgs(const
ArgList ,
if (!hasHIPStdParLibrary())
if (!HIPStdParPathArg.empty() ||
!FS.exists(Inc + "/thrust/system/hip/hipstdpar/hipstdpar_lib.hpp")) {
- D.Diag(diag::err_drv_no_hipstdpar_lib);
- return;
-}
+D.Diag(diag::err_drv_no_hipstdpar_lib);
+return;
+ }
if (!HasRocThrustLibrary && !FS.exists(Inc + "/thrust")) {
D.Diag(diag::err_drv_no_hipstdpar_thrust_lib);
return;
@@ -582,8 +582,8 @@ void RocmInstallationDetector::AddHIPIncludeArgs(const
ArgList ,
PrimPath = DriverArgs.MakeArgString(getIncludePath() + "/rocprim");
CC1Args.append({"-idirafter", ThrustPath, "-idirafter", PrimPath,
-"-idirafter", HIPStdParPath,
-"-include", "hipstdpar_lib.hpp"});
+"-idirafter", HIPStdParPath, "-include",
+"hipstdpar_lib.hpp"});
};
if (DriverArgs.hasArg(options::OPT_nogpuinc)) {
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[clang] [HIP][Driver] Automatically include `hipstdpar` forwarding header (PR #78915)
https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/78915
The forwarding header used by `hipstdpar` on AMDGPU targets is now pacakged
with `rocThrust`. This change augments the ROCm Driver component so that it can
automatically pick up the packaged header iff the user hasn't overridden it via
the dedicated flag.
>From 37453ff13fd7a61f2072069cf94615497c748089 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Sun, 21 Jan 2024 21:52:52 +
Subject: [PATCH] Add automated inclusion for the forwarding header packaged
with `rocThrust`.
---
clang/lib/Driver/ToolChains/AMDGPU.cpp | 25 +
clang/test/Driver/hipstdpar.c | 3 ++-
2 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp
b/clang/lib/Driver/ToolChains/AMDGPU.cpp
index 56f06fc5fccb7e..8a88dba562c8c0 100644
--- a/clang/lib/Driver/ToolChains/AMDGPU.cpp
+++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp
@@ -545,26 +545,35 @@ void RocmInstallationDetector::AddHIPIncludeArgs(const
ArgList ,
}
const auto HandleHipStdPar = [=, , ]() {
-if (!hasHIPStdParLibrary()) {
+StringRef Inc = getIncludePath();
+auto = D.getVFS();
+
+if (!hasHIPStdParLibrary())
+ if (!HIPStdParPathArg.empty() ||
+ !FS.exists(Inc + "/thrust/system/hip/hipstdpar/hipstdpar_lib.hpp")) {
D.Diag(diag::err_drv_no_hipstdpar_lib);
return;
}
-if (!HasRocThrustLibrary &&
-!D.getVFS().exists(getIncludePath() + "/thrust")) {
+if (!HasRocThrustLibrary && !FS.exists(Inc + "/thrust")) {
D.Diag(diag::err_drv_no_hipstdpar_thrust_lib);
return;
}
-if (!HasRocPrimLibrary &&
-!D.getVFS().exists(getIncludePath() + "/rocprim")) {
+if (!HasRocPrimLibrary && !FS.exists(Inc + "/rocprim")) {
D.Diag(diag::err_drv_no_hipstdpar_prim_lib);
return;
}
-
const char *ThrustPath;
if (HasRocThrustLibrary)
ThrustPath = DriverArgs.MakeArgString(HIPRocThrustPathArg);
else
- ThrustPath = DriverArgs.MakeArgString(getIncludePath() + "/thrust");
+ ThrustPath = DriverArgs.MakeArgString(Inc + "/thrust");
+
+const char *HIPStdParPath;
+if (hasHIPStdParLibrary())
+ HIPStdParPath = DriverArgs.MakeArgString(HIPStdParPathArg);
+else
+ HIPStdParPath = DriverArgs.MakeArgString(StringRef(ThrustPath) +
+ "/system/hip/hipstdpar");
const char *PrimPath;
if (HasRocPrimLibrary)
@@ -573,7 +582,7 @@ void RocmInstallationDetector::AddHIPIncludeArgs(const
ArgList ,
PrimPath = DriverArgs.MakeArgString(getIncludePath() + "/rocprim");
CC1Args.append({"-idirafter", ThrustPath, "-idirafter", PrimPath,
-"-idirafter", DriverArgs.MakeArgString(HIPStdParPathArg),
+"-idirafter", HIPStdParPath,
"-include", "hipstdpar_lib.hpp"});
};
diff --git a/clang/test/Driver/hipstdpar.c b/clang/test/Driver/hipstdpar.c
index 69c5b177d170cd..2f48bf6b5cf1eb 100644
--- a/clang/test/Driver/hipstdpar.c
+++ b/clang/test/Driver/hipstdpar.c
@@ -5,7 +5,8 @@
// XFAIL: target={{.*}}-scei{{.*}}
// XFAIL: target={{.*}}-sie{{.*}}
-// RUN: not %clang -### --hipstdpar -nogpulib -nogpuinc --compile %s 2>&1 | \
+// RUN: not %clang -### --hipstdpar --hipstdpar-path=/does/not/exist -nogpulib
\
+// RUN: -nogpuinc --compile %s 2>&1 | \
// RUN: FileCheck --check-prefix=HIPSTDPAR-MISSING-LIB %s
// RUN: %clang -### --hipstdpar --hipstdpar-path=%S/Inputs/hipstdpar \
// RUN: --hipstdpar-thrust-path=%S/Inputs/hipstdpar/thrust \
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[clang] Add SPIRV support to HIPAMD toolchain (PR #75357)
@@ -209,6 +210,13 @@ void AMDGCN::Linker::ConstructJob(Compilation , const
JobAction ,
if (JA.getType() == types::TY_LLVM_BC)
return constructLlvmLinkCommand(C, JA, Inputs, Output, Args);
+ if (Args.getLastArgValue(options::OPT_mcpu_EQ) == "generic") {
+llvm::opt::ArgStringList TrArgs{"--spirv-max-version=1.1",
AlexVlx wrote:
I'm not sure we want to stick with 1.1 here, the Translator goes up to 1.4 at
the moment - should we consider going to that instead?
https://github.com/llvm/llvm-project/pull/75357
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