[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)
wangpc-pp wrote: Thanks @vitalybuka for fixing the remain issues. It has been about 2 days since this PR was merged and there is no other issue, I think we finally make sized deallocation default this time! Cheers! https://github.com/llvm/llvm-project/pull/90373 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)
wangpc-pp wrote:
Thanks @vitalybuka! After some investigations, I think this PR just uncovered
the existed ASAN problem.
```cpp
#if !defined(__cpp_sized_deallocation) || __cpp_sized_deallocation < 201309L
# define _LIBCPP_HAS_NO_LANGUAGE_SIZED_DEALLOCATION
#endif
#if !defined(_LIBCPP_BUILDING_LIBRARY) && _LIBCPP_STD_VER < 14 &&
defined(_LIBCPP_HAS_NO_LANGUAGE_SIZED_DEALLOCATION)
# define _LIBCPP_HAS_NO_LIBRARY_SIZED_DEALLOCATION
#endif
#if defined(_LIBCPP_HAS_NO_LIBRARY_SIZED_DEALLOCATION) ||
defined(_LIBCPP_HAS_NO_LANGUAGE_SIZED_DEALLOCATION)
# define _LIBCPP_HAS_NO_SIZED_DEALLOCATION
#endif
template
_LIBCPP_HIDE_FROM_ABI void __do_deallocate_handle_size(void* __ptr, size_t
__size, _Args... __args) {
#ifdef _LIBCPP_HAS_NO_SIZED_DEALLOCATION
(void)__size;
return std::__libcpp_operator_delete(__ptr, __args...);
#else
return std::__libcpp_operator_delete(__ptr, __size, __args...);
#endif
}
```
The `__do_deallocate_handle_size` ignored the `__size` before this PR.
https://github.com/llvm/llvm-project/pull/90373
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[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)
wangpc-pp wrote: > > Based on my rough understanding, this is expected? > > What do you mean? > > Isn't this test needs to be updated or disabled? I think this ASAN failure is not caused by this PR because these memorys are allocated/deallocated by `memory_resource` directly, **there is nothing about `new`/`delete`**. We allocate 50 bytes via `void* ret = r1.allocate(50);` and deallocate 1 byte via `r1.deallocate(ret, 1);` and that's the reason why ASAN failed, because the size of the allocated type (50 bytes) and the size of the deallocated type (1 byte) are really not matched. I don't know if this is what we want to test, if so, we may add `// UNSUPPORTED: asan` to skip this test in ASAN builds. cc @ldionne @Quuxplusone https://github.com/llvm/llvm-project/pull/90373 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)
wangpc-pp wrote:
> This one is broken https://lab.llvm.org/buildbot/#/builders/168/builds/20461
The broken case is:
```cpp
void test_allocate_deallocate() {
std::pmr::memory_resource& r1 = *std::pmr::new_delete_resource();
globalMemCounter.reset();
void* ret = r1.allocate(50);
assert(ret);
ASSERT_WITH_LIBRARY_INTERNAL_ALLOCATIONS(globalMemCounter.checkOutstandingNewEq(1));
ASSERT_WITH_LIBRARY_INTERNAL_ALLOCATIONS(globalMemCounter.checkLastNewSizeEq(50));
r1.deallocate(ret, 1);
assert(globalMemCounter.checkOutstandingNewEq(0));
ASSERT_WITH_LIBRARY_INTERNAL_ALLOCATIONS(globalMemCounter.checkDeleteCalledEq(1));
}
```
The errors are:
```
# .---command stderr
# | =
# | ==3452201==ERROR: AddressSanitizer: new-delete-type-mismatch on
0x50600020 in thread T0:
# | object passed to delete has wrong type:
# | size of the allocated type: 50 bytes;
# | size of the deallocated type: 1 bytes.
# | #0 0x565094abbd02
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14ad02)
# | #1 0x565094abe168
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14d168)
# | #2 0x565094abd941
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14c941)
# | #3 0x565094abda24
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14ca24)
# | #4 0x7f8643c2814f (/lib/x86_64-linux-gnu/libc.so.6+0x2814f) (BuildId:
b20cbdb62d7717c13dc61a48b7b2e673a7edf233)
# | #5 0x7f8643c28208 (/lib/x86_64-linux-gnu/libc.so.6+0x28208) (BuildId:
b20cbdb62d7717c13dc61a48b7b2e673a7edf233)
# | #6 0x5650949dbed4
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x6aed4)
# |
# | 0x50600020 is located 0 bytes inside of 50-byte region
[0x50600020,0x50600052)
# | allocated by thread T0 here:
# | #0 0x565094abb09d
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14a09d)
# | #1 0x565094abe098
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14d098)
# | #2 0x565094abd83f
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14c83f)
# | #3 0x565094abda24
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14ca24)
# | #4 0x7f8643c2814f (/lib/x86_64-linux-gnu/libc.so.6+0x2814f) (BuildId:
b20cbdb62d7717c13dc61a48b7b2e673a7edf233)
# |
# | SUMMARY: AddressSanitizer: new-delete-type-mismatch
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14ad02)
# | ==3452201==HINT: if you don't care about these errors you may set
ASAN_OPTIONS=new_delete_type_mismatch=0
# | ==3452201==ABORTING
# `-
# error: command failed with exit status: 1
```
Based on my rough understanding, this is expected? Because we allocate 50 bytes
via `void* ret = r1.allocate(50);` and deallocate 1 byte via
`r1.deallocate(ret, 1);`.
https://github.com/llvm/llvm-project/pull/90373
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[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/90373 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/90373
>From a18f57e23c0d4fd23647eb2ef610352e402b45f6 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang
Date: Fri, 26 Apr 2024 16:59:12 +0800
Subject: [PATCH] [clang] Enable sized deallocation by default in C++14 onwards
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
This is another try of https://reviews.llvm.org/D112921.
The original commit cf5a8b4 was reverted by 2e5035a due to some
failures (see #83774).
Fixes #60061
---
.../clangd/unittests/FindTargetTests.cpp | 4 +-
.../checkers/misc/new-delete-overloads.cpp| 10 -
clang/docs/ReleaseNotes.rst | 5 +
clang/include/clang/Driver/Options.td | 8 +-
clang/lib/Driver/ToolChains/Clang.cpp | 13 +-
clang/lib/Driver/ToolChains/Darwin.cpp| 58 -
clang/lib/Driver/ToolChains/Darwin.h | 4 +
clang/lib/Driver/ToolChains/ZOS.cpp | 6 +
clang/test/AST/ast-dump-expr-json.cpp | 2 +-
clang/test/AST/ast-dump-expr.cpp | 2 +-
clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +-
.../basic.stc.dynamic.deallocation/p2.cpp | 2 +-
clang/test/CXX/drs/cwg292.cpp | 17 +-
.../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +-
.../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +-
.../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +-
.../CodeGenCXX/cxx2a-destroying-delete.cpp| 4 +-
clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +-
clang/test/CodeGenCXX/delete.cpp | 12 +-
clang/test/CodeGenCXX/dllimport.cpp | 4 +-
clang/test/CodeGenCXX/new.cpp | 6 +-
.../coro-aligned-alloc-2.cpp | 2 -
.../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 -
clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +-
clang/test/CodeGenCoroutines/pr56919.cpp | 9 +-
clang/test/Lexer/cxx-features.cpp | 20 +-
clang/test/PCH/cxx1z-aligned-alloc.cpp| 10 +-
clang/test/SemaCXX/MicrosoftExtensions.cpp| 8 +-
.../SemaCXX/builtin-operator-new-delete.cpp | 2 +-
.../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +-
.../unavailable_aligned_allocation.cpp| 15 +-
clang/tools/clang-repl/CMakeLists.txt | 43 +++
clang/unittests/Interpreter/CMakeLists.txt| 43 +++
.../StaticAnalyzer/CallEventTest.cpp | 2 +-
clang/www/cxx_status.html | 11 +-
.../support.dynamic/libcpp_deallocate.sh.cpp | 3 +
.../sized_delete_array14.pass.cpp | 8 +-
.../new.delete.single/sized_delete14.pass.cpp | 8 +-
42 files changed, 523 insertions(+), 113 deletions(-)
diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 0b2273f0a9a6e..3220a5a6a9825 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -836,7 +836,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
[[delete]] x;
}
)cpp";
- EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+ // Sized deallocation is enabled by default in C++14 onwards.
+ EXPECT_DECLS("CXXDeleteExpr",
+ "void operator delete(void *, unsigned long) noexcept");
}
TEST_F(TargetDeclTest, DependentExprs) {
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e1..f86fe8a4c5b14 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
// CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has
no matching declaration of 'operator delete' at the same scope
void *operator new(size_t size) noexcept(false);
-struct T {
- // Sized deallocations are not enabled by default, and so this new/delete
pair
- // does not match. However, we expect only one warning, for the new, because
- // the operator delete is a placement delete and we do not warn on
mismatching
- // placement operations.
- // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new'
has no matching declaration of 'operator delete' at the same scope
- void *operator new(size_t size) noexcept;
- void operator delete(void *ptr, size_t) noexcept; // ok only if sized
deallocation is enabled
-};
-
struct U {
void *operator new(size_t size) noexcept;
void operator delete(void *ptr)
[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)
wangpc-pp wrote: Please review this PR as all noticable issues have been fixed I think. https://github.com/llvm/llvm-project/pull/90373 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/90373
>From fd015302585fc8149811868636cb0da5c422cf7a Mon Sep 17 00:00:00 2001
From: Pengcheng Wang
Date: Fri, 26 Apr 2024 16:59:12 +0800
Subject: [PATCH] [clang] Enable sized deallocation by default in C++14 onwards
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
This is another try of https://reviews.llvm.org/D112921.
The original commit cf5a8b4 was reverted by 2e5035a due to some
failures (see #83774).
Fixes #60061
---
.../clangd/unittests/FindTargetTests.cpp | 4 +-
.../checkers/misc/new-delete-overloads.cpp| 10 -
clang/docs/ReleaseNotes.rst | 5 +
clang/include/clang/Driver/Options.td | 8 +-
clang/lib/Driver/ToolChains/Clang.cpp | 13 +-
clang/lib/Driver/ToolChains/Darwin.cpp| 58 -
clang/lib/Driver/ToolChains/Darwin.h | 4 +
clang/lib/Driver/ToolChains/ZOS.cpp | 6 +
clang/test/AST/ast-dump-expr-json.cpp | 2 +-
clang/test/AST/ast-dump-expr.cpp | 2 +-
clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +-
.../basic.stc.dynamic.deallocation/p2.cpp | 2 +-
clang/test/CXX/drs/cwg292.cpp | 17 +-
.../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +-
.../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +-
.../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +-
.../CodeGenCXX/cxx2a-destroying-delete.cpp| 4 +-
clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +-
clang/test/CodeGenCXX/delete.cpp | 12 +-
clang/test/CodeGenCXX/dllimport.cpp | 4 +-
clang/test/CodeGenCXX/new.cpp | 6 +-
.../coro-aligned-alloc-2.cpp | 2 -
.../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 -
clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +-
clang/test/CodeGenCoroutines/pr56919.cpp | 9 +-
clang/test/Lexer/cxx-features.cpp | 20 +-
clang/test/PCH/cxx1z-aligned-alloc.cpp| 10 +-
clang/test/SemaCXX/MicrosoftExtensions.cpp| 8 +-
.../SemaCXX/builtin-operator-new-delete.cpp | 2 +-
.../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +-
.../unavailable_aligned_allocation.cpp| 15 +-
clang/tools/clang-repl/CMakeLists.txt | 43 +++
clang/unittests/Interpreter/CMakeLists.txt| 43 +++
.../StaticAnalyzer/CallEventTest.cpp | 2 +-
clang/www/cxx_status.html | 11 +-
.../support.dynamic/libcpp_deallocate.sh.cpp | 3 +
.../sized_delete_array14.pass.cpp | 8 +-
.../new.delete.single/sized_delete14.pass.cpp | 8 +-
42 files changed, 523 insertions(+), 113 deletions(-)
diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 0b2273f0a9a6e..3220a5a6a9825 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -836,7 +836,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
[[delete]] x;
}
)cpp";
- EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+ // Sized deallocation is enabled by default in C++14 onwards.
+ EXPECT_DECLS("CXXDeleteExpr",
+ "void operator delete(void *, unsigned long) noexcept");
}
TEST_F(TargetDeclTest, DependentExprs) {
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e1..f86fe8a4c5b14 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
// CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has
no matching declaration of 'operator delete' at the same scope
void *operator new(size_t size) noexcept(false);
-struct T {
- // Sized deallocations are not enabled by default, and so this new/delete
pair
- // does not match. However, we expect only one warning, for the new, because
- // the operator delete is a placement delete and we do not warn on
mismatching
- // placement operations.
- // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new'
has no matching declaration of 'operator delete' at the same scope
- void *operator new(size_t size) noexcept;
- void operator delete(void *ptr, size_t) noexcept; // ok only if sized
deallocation is enabled
-};
-
struct U {
void *operator new(size_t size) noexcept;
void operator delete(void *ptr)
[clang] [clang] Introduce `SemaRISCV` (PR #92682)
https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/92682 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
@@ -112,10 +112,10 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s +; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s wangpc-pp wrote: Same here. https://github.com/llvm/llvm-project/pull/91556 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
wangpc-pp wrote:
You may need to move these tests out of experimental space.
https://github.com/llvm/llvm-project/pull/91556
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[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
https://github.com/wangpc-pp approved this pull request. LGTM. Thanks! https://github.com/llvm/llvm-project/pull/91556 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] Introduce `SemaRISCV` (PR #92682)
wangpc-pp wrote: I think it's a good rewrite. Added more RISCV guys. https://github.com/llvm/llvm-project/pull/92682 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Remove unneeded multiply in RISCV CodeGenTypes (PR #92644)
https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/92644 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] Introduce `SemaRISCV` (PR #92682)
wangpc-pp wrote: Is it a NFC? https://github.com/llvm/llvm-project/pull/92682 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)
=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: wangpc-pp wrote: I'd like to see the support of KunMingHu, but please hold this PR and wait for the finalization of KunMingHu's architecture. https://github.com/llvm/llvm-project/pull/90392 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)
wangpc-pp wrote: > > > @dyung Can you help me to comfirm whether the Windows builder is passing > > > now? I don't have such environment. Thanks in advance! > > > > > > Sure, I'll try it on our internal builder and see if it passes and let you > > know the result. > > I can confirm that this change builds successfully on our Windows > configuration. Thanks a lot, that was quick! There is another AddressSanitizer issue that may possibly be fixed by https://github.com/llvm/llvm-project/pull/90292. cc @vitalybuka https://github.com/llvm/llvm-project/pull/90373 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)
wangpc-pp wrote: @dyung Can you help me to comfirm whether the Windows builder is passing now? I don't have such environment. Thanks in advance! https://github.com/llvm/llvm-project/pull/90373 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/90373
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
This is another try of https://reviews.llvm.org/D112921.
The original commit cf5a8b4 was reverted by 2e5035a due to some
failures (see #83774).
Fixes #60061
>From cc722438155619cb0524eb26191be0465ccddbf0 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang
Date: Fri, 26 Apr 2024 16:59:12 +0800
Subject: [PATCH] [clang] Enable sized deallocation by default in C++14 onwards
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
This is another try of https://reviews.llvm.org/D112921.
The original commit cf5a8b4 was reverted by 2e5035a due to some
failures (see #83774).
Fixes #60061
---
.../clangd/unittests/FindTargetTests.cpp | 4 +-
.../checkers/misc/new-delete-overloads.cpp| 10 -
clang/docs/ReleaseNotes.rst | 5 +
clang/include/clang/Driver/Options.td | 8 +-
clang/lib/Driver/ToolChains/Clang.cpp | 13 +-
clang/lib/Driver/ToolChains/Darwin.cpp| 58 -
clang/lib/Driver/ToolChains/Darwin.h | 4 +
clang/lib/Driver/ToolChains/ZOS.cpp | 6 +
clang/test/AST/ast-dump-expr-json.cpp | 2 +-
clang/test/AST/ast-dump-expr.cpp | 2 +-
clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +-
.../basic.stc.dynamic.deallocation/p2.cpp | 2 +-
clang/test/CXX/drs/cwg292.cpp | 17 +-
.../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +-
.../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +-
.../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +-
.../CodeGenCXX/cxx2a-destroying-delete.cpp| 4 +-
clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +-
clang/test/CodeGenCXX/delete.cpp | 12 +-
clang/test/CodeGenCXX/dllimport.cpp | 4 +-
clang/test/CodeGenCXX/new.cpp | 6 +-
.../coro-aligned-alloc-2.cpp | 2 -
.../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 -
clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +-
clang/test/CodeGenCoroutines/pr56919.cpp | 9 +-
clang/test/Lexer/cxx-features.cpp | 20 +-
clang/test/PCH/cxx1z-aligned-alloc.cpp| 10 +-
clang/test/SemaCXX/MicrosoftExtensions.cpp| 8 +-
.../SemaCXX/builtin-operator-new-delete.cpp | 2 +-
.../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +-
.../unavailable_aligned_allocation.cpp| 15 +-
clang/tools/clang-repl/CMakeLists.txt | 43 +++
clang/unittests/Interpreter/CMakeLists.txt| 43 +++
.../StaticAnalyzer/CallEventTest.cpp | 2 +-
clang/www/cxx_status.html | 11 +-
.../support.dynamic/libcpp_deallocate.sh.cpp | 3 +
.../sized_delete_array14.pass.cpp | 8 +-
.../new.delete.single/sized_delete14.pass.cpp | 8 +-
42 files changed, 523 insertions(+), 113 deletions(-)
diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 799a549ff0816e..88aae2729904f4 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
[[delete]] x;
}
)cpp";
- EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+ // Sized deallocation is enabled by default in C++14 onwards.
+ EXPECT_DECLS("CXXDeleteExpr",
+ "void operator delete(void *, unsigned long) noexcept");
}
TEST_F(TargetDeclTest, DependentExprs) {
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e19..f86fe8a4c5b14f 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
// CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has
no matching declaration of 'operator delete' at the same scope
void *operator new(size_t size) noexcept(false);
-struct T {
- // Sized deallocations are not enabled by default, and so this new/delete
pair
- // does not match. However, we expect only one warning, for the new, because
- // the operator delete is a placement delete and we do not warn on
mismatching
- // placement operations.
- // CHECK-MESSAGES: :[[@LINE+1]]:9: warning:
[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)
wangpc-pp wrote: I don't know why spr added so many reviewers... sorry for bothering. https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q?itial=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.4 --- clang/test/Driver/riscv-cpus.c| 319 ++ clang/test/Misc/target-invalid-cpu-note.c | 8 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 224 ++- 3 files changed, 539 insertions(+), 12 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index ff2bd6f7c8ba34..a285f0f9c41f54 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -302,3 +302,322 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// Check profile CPUs + +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s +// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s +// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s +// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+m" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+a" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+f" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+d" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+c" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s +// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare" +// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s +// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature"
[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
wangpc-pp wrote: > This change is also causing a failure on our internal Windows builder, and a > public Windows bot: > https://lab.llvm.org/buildbot/#/builders/119/builds/17634 > ``` > 88.872 [191/66/4550] Linking CXX executable bin\clang-repl.exe > FAILED: bin/clang-repl.exe > cmd.exe /C "cd . && "C:\Program Files\CMake\bin\cmake.exe" -E vs_link_exe > --intdir=tools\clang\tools\clang-repl\CMakeFiles\clang-repl.dir > --rc=C:\PROGRA~2\WINDOW~4\10\bin\100226~1.0\x64\rc.exe > --mt=C:\PROGRA~2\WINDOW~4\10\bin\100226~1.0\x64\mt.exe --manifests -- > C:\PROGRA~1\MICROS~2\2022\COMMUN~1\VC\Tools\MSVC\1439~1.335\bin\Hostx64\x64\link.exe > /nologo @CMakeFiles\clang-repl.rsp /out:bin\clang-repl.exe > /implib:lib\clang-repl.lib /pdb:bin\clang-repl.pdb /version:0.0 /machine:x64 > /STACK:1000 /INCREMENTAL:NO /subsystem:console > /EXPORT:??_7type_info@@6B@ > /EXPORT:?__type_info_root_node@@3U__type_info_node@@A > /EXPORT:?nothrow@std@@3Unothrow_t@1@B /EXPORT:_Init_thread_abort > /EXPORT:_Init_thread_epoch /EXPORT:_Init_thread_footer > /EXPORT:_Init_thread_header /EXPORT:_tls_index /EXPORT:??2@YAPEAX_K@Z > /EXPORT:??3@YAXPEAX@Z /EXPORT:??_U@YAPEAX_K@Z /EXPORT:??_V@YAXPEAX@Z > /EXPORT:??3@YAXPEAX_K@Z > /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z > /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z > /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@N@Z > /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z > /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z > > /EXPORT:??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z > > /EXPORT:??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@PEBD@Z > /EXPORT:?_Facet_Register@std@@YAXPEAV_Facet_base@1@@Z -Wl,--long-plt && cd > ." > LINK: command > "C:\PROGRA~1\MICROS~2\2022\COMMUN~1\VC\Tools\MSVC\1439~1.335\bin\Hostx64\x64\link.exe > /nologo @CMakeFiles\clang-repl.rsp /out:bin\clang-repl.exe > /implib:lib\clang-repl.lib /pdb:bin\clang-repl.pdb /version:0.0 /machine:x64 > /STACK:1000 /INCREMENTAL:NO /subsystem:console /EXPORT:??_7type_info@@6B@ > /EXPORT:?__type_info_root_node@@3U__type_info_node@@A > /EXPORT:?nothrow@std@@3Unothrow_t@1@B /EXPORT:_Init_thread_abort > /EXPORT:_Init_thread_epoch /EXPORT:_Init_thread_footer > /EXPORT:_Init_thread_header /EXPORT:_tls_index /EXPORT:??2@YAPEAX_K@Z > /EXPORT:??3@YAXPEAX@Z /EXPORT:??_U@YAPEAX_K@Z /EXPORT:??_V@YAXPEAX@Z > /EXPORT:??3@YAXPEAX_K@Z > /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z > /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z > /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@N@Z > /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z > /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z > > /EXPORT:??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z > > /EXPORT:??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@PEBD@Z > /EXPORT:?_Facet_Register@std@@YAXPEAV_Facet_base@1@@Z -Wl,--long-plt > /MANIFEST /MANIFESTFILE:bin\clang-repl.exe.manifest" failed (exit code 1120) > with the following output: > LINK : warning LNK4044: unrecognized option '/Wl,--long-plt'; ignored >Creating library lib\clang-repl.lib and object lib\clang-repl.exp > LIBCMT.lib(initializers.obj) : warning LNK4098: defaultlib 'msvcrt.lib' > conflicts with use of other libs; use /NODEFAULTLIB:library > LINK : warning LNK4217: symbol 'free' defined in 'libucrt.lib(free.obj)' is > imported by 'zlibstatic.lib(zutil.obj)' in function 'zcfree' > LINK : warning LNK4217: symbol 'malloc' defined in 'libucrt.lib(malloc.obj)' > is imported by 'zlibstatic.lib(zutil.obj)' in function 'zcalloc' > clang-repl.exp : error LNK2001: unresolved external symbol "public: class > std::basic_ostream > & __cdecl > std::basic_ostream >::operator<<(float)" > (??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z) > clang-repl.exp : error LNK2001: unresolved external symbol "public: class > std::basic_ostream > & __cdecl > std::basic_ostream >::operator<<(class > std::basic_ostream > & (__cdecl*)(class > std::basic_ostream > &))" > (??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z) > clang-repl.exp : error LNK2001: unresolved external symbol "public: class > std::basic_ostream > & __cdecl > std::basic_ostream >::operator<<(void > const *)" (??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z) > bin\clang-repl.exe : fatal error LNK1120: 3 unresolved externals > > ``` It seems that we need to remove these symbols from the CMakeLists.txt of clang-repl. https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
wangpc-pp wrote: > Lets revert #90299 to recover bots before the weekend. > Many thanks for reverting it and fixing one of the failures! https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/89051 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)
@@ -0,0 +1,25 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -disable-O0-optnone
-emit-llvm \
+// RUN: %s -o - | opt -S -passes=mem2reg | FileCheck %s
+
+// CHECK-LABEL: define dso_local half @test_convert_from_bf16_to_fp16(
+// CHECK-SAME: bfloat noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[FPEXT:%.*]] = fpext bfloat [[A]] to float
+// CHECK-NEXT:[[FPTRUNC:%.*]] = fptrunc float [[FPEXT]] to half
+// CHECK-NEXT:ret half [[FPTRUNC]]
+//
+_Float16 test_convert_from_bf16_to_fp16(__bf16 a) {
+return (_Float16)a;
+}
+
+// CHECK-LABEL: define dso_local bfloat @test_convert_from_fp16_to_bf16(
+// CHECK-SAME: half noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[FPEXT:%.*]] = fpext half [[A]] to float
+// CHECK-NEXT:[[FPTRUNC:%.*]] = fptrunc float [[FPEXT]] to bfloat
+// CHECK-NEXT:ret bfloat [[FPTRUNC]]
+//
+__bf16 test_convert_from_fp16_to_bf16(_Float16 a) {
+return (__bf16)a;
+}
+
wangpc-pp wrote:
Vector tests are moved to HIP target now as the IRs are wierd in X86.
https://github.com/llvm/llvm-project/pull/89051
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[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)
@@ -0,0 +1,165 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -disable-O0-optnone
-emit-llvm \
+// RUN: %s -o - | opt -S -passes=mem2reg | FileCheck %s
+
+// CHECK-LABEL: define dso_local half @test_convert_from_bf16_to_fp16(
+// CHECK-SAME: bfloat noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[FPEXT:%.*]] = fpext bfloat [[A]] to float
+// CHECK-NEXT:[[FPTRUNC:%.*]] = fptrunc float [[FPEXT]] to half
+// CHECK-NEXT:ret half [[FPTRUNC]]
+//
+_Float16 test_convert_from_bf16_to_fp16(__bf16 a) {
+return (_Float16)a;
+}
+
+// CHECK-LABEL: define dso_local bfloat @test_convert_from_fp16_to_bf16(
+// CHECK-SAME: half noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[FPEXT:%.*]] = fpext half [[A]] to float
+// CHECK-NEXT:[[FPTRUNC:%.*]] = fptrunc float [[FPEXT]] to bfloat
+// CHECK-NEXT:ret bfloat [[FPTRUNC]]
+//
+__bf16 test_convert_from_fp16_to_bf16(_Float16 a) {
+return (__bf16)a;
+}
+
+typedef _Float16 half2 __attribute__((ext_vector_type(2)));
+typedef _Float16 half4 __attribute__((ext_vector_type(4)));
+
+typedef __bf16 bfloat2 __attribute__((ext_vector_type(2)));
+typedef __bf16 bfloat4 __attribute__((ext_vector_type(4)));
+
+// CHECK-LABEL: define dso_local i32 @test_cast_from_half2_to_bfloat2(
+// CHECK-SAME: i32 noundef [[IN_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca <2 x bfloat>, align 4
+// CHECK-NEXT:[[IN:%.*]] = alloca <2 x half>, align 4
+// CHECK-NEXT:store i32 [[IN_COERCE]], ptr [[IN]], align 4
+// CHECK-NEXT:[[IN1:%.*]] = load <2 x half>, ptr [[IN]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <2 x half> [[IN1]] to <2 x bfloat>
+// CHECK-NEXT:store <2 x bfloat> [[TMP0]], ptr [[RETVAL]], align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4
+// CHECK-NEXT:ret i32 [[TMP1]]
+//
+bfloat2 test_cast_from_half2_to_bfloat2(half2 in) {
+ return (bfloat2)in;
+}
+
+
+// CHECK-LABEL: define dso_local double @test_cast_from_half4_to_bfloat4(
+// CHECK-SAME: double noundef [[IN_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca <4 x bfloat>, align 8
+// CHECK-NEXT:[[IN:%.*]] = alloca <4 x half>, align 8
+// CHECK-NEXT:store double [[IN_COERCE]], ptr [[IN]], align 8
+// CHECK-NEXT:[[IN1:%.*]] = load <4 x half>, ptr [[IN]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <4 x half> [[IN1]] to <4 x bfloat>
+// CHECK-NEXT:store <4 x bfloat> [[TMP0]], ptr [[RETVAL]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, ptr [[RETVAL]], align 8
+// CHECK-NEXT:ret double [[TMP1]]
+//
+bfloat4 test_cast_from_half4_to_bfloat4(half4 in) {
+ return (bfloat4)in;
+}
+
+// CHECK-LABEL: define dso_local i32 @test_cast_from_bfloat2_to_half2(
+// CHECK-SAME: i32 noundef [[IN_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca <2 x half>, align 4
+// CHECK-NEXT:[[IN:%.*]] = alloca <2 x bfloat>, align 4
+// CHECK-NEXT:store i32 [[IN_COERCE]], ptr [[IN]], align 4
+// CHECK-NEXT:[[IN1:%.*]] = load <2 x bfloat>, ptr [[IN]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <2 x bfloat> [[IN1]] to <2 x half>
+// CHECK-NEXT:store <2 x half> [[TMP0]], ptr [[RETVAL]], align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4
+// CHECK-NEXT:ret i32 [[TMP1]]
+//
+half2 test_cast_from_bfloat2_to_half2(bfloat2 in) {
+ return (half2)in;
+}
+
+
+// CHECK-LABEL: define dso_local double @test_cast_from_bfloat4_to_half4(
+// CHECK-SAME: double noundef [[IN_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca <4 x half>, align 8
+// CHECK-NEXT:[[IN:%.*]] = alloca <4 x bfloat>, align 8
+// CHECK-NEXT:store double [[IN_COERCE]], ptr [[IN]], align 8
+// CHECK-NEXT:[[IN1:%.*]] = load <4 x bfloat>, ptr [[IN]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <4 x bfloat> [[IN1]] to <4 x half>
+// CHECK-NEXT:store <4 x half> [[TMP0]], ptr [[RETVAL]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, ptr [[RETVAL]], align 8
+// CHECK-NEXT:ret double [[TMP1]]
+//
+half4 test_cast_from_bfloat4_to_half4(bfloat4 in) {
+ return (half4)in;
+}
+
+
+// CHECK-LABEL: define dso_local i32 @test_convertvector_from_half2_to_bfloat2(
+// CHECK-SAME: i32 noundef [[IN_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca <2 x bfloat>, align 4
+// CHECK-NEXT:[[IN:%.*]] = alloca <2 x half>, align 4
+// CHECK-NEXT:store i32 [[IN_COERCE]], ptr [[IN]], align 4
+// CHECK-NEXT:[[IN1:%.*]] = load <2 x half>, ptr [[IN]], align 4
+// CHECK-NEXT:[[FPEXT:%.*]] = fpext <2 x half> [[IN1]] to <2 x float>
+// CHECK-NEXT:[[FPTRUNC:%.*]] = fptrunc <2 x float> [[FPEXT]] to <2 x
bfloat>
+// CHECK-NEXT:store <2 x bfloat> [[FPTRUNC]], ptr [[RETVAL]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load
[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q?itial=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.4 --- clang/test/Driver/riscv-cpus.c| 319 ++ clang/test/Misc/target-invalid-cpu-note.c | 8 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 224 ++- 3 files changed, 539 insertions(+), 12 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index ff2bd6f7c8ba34..a285f0f9c41f54 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -302,3 +302,322 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// Check profile CPUs + +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s +// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s +// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s +// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+m" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+a" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+f" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+d" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+c" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s +// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare" +// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s +// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature"
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)
@@ -138,6 +155,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
/// initializeProperties().
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
+ RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
+
wangpc-pp wrote:
Curently no, but we can support them in `RISCVISAInfo::updateCombination()`.
And I don't know if we need `getRISCVProfile` function, maybe we should remove
it because there is no user.
https://github.com/llvm/llvm-project/pull/84877
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[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q?itial=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.4 --- clang/test/Driver/riscv-cpus.c| 319 ++ clang/test/Misc/target-invalid-cpu-note.c | 8 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 224 ++- 3 files changed, 539 insertions(+), 12 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index ff2bd6f7c8ba34..a285f0f9c41f54 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -302,3 +302,322 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// Check profile CPUs + +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s +// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s +// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s +// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+m" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+a" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+f" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+d" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+c" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s +// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare" +// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s +// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature"
[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q?itial=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.4 --- clang/test/Driver/riscv-cpus.c| 319 ++ clang/test/Misc/target-invalid-cpu-note.c | 8 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 224 ++- 3 files changed, 539 insertions(+), 12 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index ff2bd6f7c8ba34..a285f0f9c41f54 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -302,3 +302,322 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// Check profile CPUs + +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s +// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s +// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s +// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+m" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+a" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+f" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+d" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+c" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s +// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare" +// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s +// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature"
[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)
wangpc-pp wrote: > Do you see any disadvantage to going back to adding a feature for the > profiles? Of course not, I will revise this patch tomorrow. Thanks for discussing this! (I missed the sync-up meeting because I forgot the daylight saving...) https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)
wangpc-pp wrote: Gentle ping. https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From 2ed73672a548b77a36675343b420ef57266e46ab Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH] [clang] Enable sized deallocation by default in C++14 onwards
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
Differential Revision: https://reviews.llvm.org/D112921
---
.../clangd/unittests/FindTargetTests.cpp | 4 +-
.../checkers/misc/new-delete-overloads.cpp| 10 -
clang/docs/ReleaseNotes.rst | 5 +
clang/include/clang/Driver/Options.td | 8 +-
clang/lib/Driver/ToolChains/Clang.cpp | 13 +-
clang/lib/Driver/ToolChains/Darwin.cpp| 58 -
clang/lib/Driver/ToolChains/Darwin.h | 4 +
clang/lib/Driver/ToolChains/ZOS.cpp | 6 +
clang/test/AST/ast-dump-expr-json.cpp | 2 +-
clang/test/AST/ast-dump-expr.cpp | 2 +-
clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +-
.../basic.stc.dynamic.deallocation/p2.cpp | 2 +-
clang/test/CXX/drs/cwg292.cpp | 17 +-
.../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +-
.../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +-
.../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +-
.../CodeGenCXX/cxx2a-destroying-delete.cpp| 4 +-
clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +-
clang/test/CodeGenCXX/delete.cpp | 12 +-
clang/test/CodeGenCXX/dllimport.cpp | 4 +-
clang/test/CodeGenCXX/new.cpp | 6 +-
.../coro-aligned-alloc-2.cpp | 2 -
.../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 -
clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +-
clang/test/CodeGenCoroutines/pr56919.cpp | 9 +-
clang/test/Lexer/cxx-features.cpp | 20 +-
clang/test/PCH/cxx1z-aligned-alloc.cpp| 10 +-
clang/test/SemaCXX/MicrosoftExtensions.cpp| 8 +-
.../SemaCXX/builtin-operator-new-delete.cpp | 2 +-
.../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +-
.../unavailable_aligned_allocation.cpp| 15 +-
clang/tools/clang-repl/CMakeLists.txt | 59 +
clang/unittests/Interpreter/CMakeLists.txt| 59 +
.../StaticAnalyzer/CallEventTest.cpp | 2 +-
clang/www/cxx_status.html | 11 +-
.../support.dynamic/libcpp_deallocate.sh.cpp | 3 +
.../sized_delete_array14.pass.cpp | 8 +-
.../new.delete.single/sized_delete14.pass.cpp | 8 +-
42 files changed, 555 insertions(+), 113 deletions(-)
diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 799a549ff0816e..88aae2729904f4 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
[[delete]] x;
}
)cpp";
- EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+ // Sized deallocation is enabled by default in C++14 onwards.
+ EXPECT_DECLS("CXXDeleteExpr",
+ "void operator delete(void *, unsigned long) noexcept");
}
TEST_F(TargetDeclTest, DependentExprs) {
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e19..f86fe8a4c5b14f 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
// CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has
no matching declaration of 'operator delete' at the same scope
void *operator new(size_t size) noexcept(false);
-struct T {
- // Sized deallocations are not enabled by default, and so this new/delete
pair
- // does not match. However, we expect only one warning, for the new, because
- // the operator delete is a placement delete and we do not warn on
mismatching
- // placement operations.
- // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new'
has no matching declaration of 'operator delete' at the same scope
- void *operator new(size_t size) noexcept;
- void operator delete(void *ptr, size_t) noexcept; // ok only if sized
deallocation is enabled
-};
-
struct U {
void *operator new(size_t size) noexcept;
void operator delete(void *ptr) noexcept;
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index
[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)
https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/89684 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)
@@ -0,0 +1,194 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -target-feature +fullbf16 -S -emit-llvm %s -o - | FileCheck %s wangpc-pp wrote: ```suggestion // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -target-feature +fullbf16 -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s ``` We can run `mem2reg` to reduce CHECKs. https://github.com/llvm/llvm-project/pull/89051 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)
https://github.com/wangpc-pp commented: I think this patch doesn't need to be stacked on #89335. https://github.com/llvm/llvm-project/pull/89684 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)
@@ -1,12 +1,12 @@ -//===-- RISCVISAInfo.cpp - RISC-V Arch String Parser *- C++ -*-===// wangpc-pp wrote: We shouldn't remove `*- C++ -*` here I think, it's for editors like Emacs. https://github.com/llvm/llvm-project/pull/89684 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/89684 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From f84c6c7a108d179ffa7f5ec423d852cb667e0f33 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH] [clang] Enable sized deallocation by default in C++14 onwards
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
Differential Revision: https://reviews.llvm.org/D112921
---
.../clangd/unittests/FindTargetTests.cpp | 4 +-
.../checkers/misc/new-delete-overloads.cpp| 10 -
clang/docs/ReleaseNotes.rst | 5 +
clang/include/clang/Driver/Options.td | 8 +-
clang/lib/Driver/ToolChains/Clang.cpp | 13 +-
clang/lib/Driver/ToolChains/Darwin.cpp| 58 -
clang/lib/Driver/ToolChains/Darwin.h | 4 +
clang/lib/Driver/ToolChains/ZOS.cpp | 6 +
clang/test/AST/ast-dump-expr-json.cpp | 2 +-
clang/test/AST/ast-dump-expr.cpp | 2 +-
clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +-
.../basic.stc.dynamic.deallocation/p2.cpp | 2 +-
clang/test/CXX/drs/cwg292.cpp | 17 +-
.../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +-
.../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +-
.../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +-
.../CodeGenCXX/cxx2a-destroying-delete.cpp| 4 +-
clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +-
clang/test/CodeGenCXX/delete.cpp | 12 +-
clang/test/CodeGenCXX/dllimport.cpp | 4 +-
clang/test/CodeGenCXX/new.cpp | 6 +-
.../coro-aligned-alloc-2.cpp | 2 -
.../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 -
clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +-
clang/test/CodeGenCoroutines/pr56919.cpp | 9 +-
clang/test/Lexer/cxx-features.cpp | 20 +-
clang/test/PCH/cxx1z-aligned-alloc.cpp| 10 +-
clang/test/SemaCXX/MicrosoftExtensions.cpp| 8 +-
.../SemaCXX/builtin-operator-new-delete.cpp | 2 +-
.../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +-
.../unavailable_aligned_allocation.cpp| 15 +-
clang/tools/clang-repl/CMakeLists.txt | 59 +
clang/unittests/Interpreter/CMakeLists.txt| 59 +
.../StaticAnalyzer/CallEventTest.cpp | 2 +-
clang/www/cxx_status.html | 11 +-
.../support.dynamic/libcpp_deallocate.sh.cpp | 3 +
.../sized_delete_array14.pass.cpp | 8 +-
.../new.delete.single/sized_delete14.pass.cpp | 8 +-
42 files changed, 555 insertions(+), 113 deletions(-)
diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 0af6036734ba53..1b7b96281dfaa5 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
[[delete]] x;
}
)cpp";
- EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+ // Sized deallocation is enabled by default in C++14 onwards.
+ EXPECT_DECLS("CXXDeleteExpr",
+ "void operator delete(void *, unsigned long) noexcept");
}
TEST_F(TargetDeclTest, DependentExprs) {
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e19..f86fe8a4c5b14f 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
// CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has
no matching declaration of 'operator delete' at the same scope
void *operator new(size_t size) noexcept(false);
-struct T {
- // Sized deallocations are not enabled by default, and so this new/delete
pair
- // does not match. However, we expect only one warning, for the new, because
- // the operator delete is a placement delete and we do not warn on
mismatching
- // placement operations.
- // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new'
has no matching declaration of 'operator delete' at the same scope
- void *operator new(size_t size) noexcept;
- void operator delete(void *ptr, size_t) noexcept; // ok only if sized
deallocation is enabled
-};
-
struct U {
void *operator new(size_t size) noexcept;
void operator delete(void *ptr) noexcept;
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)
wangpc-pp wrote: Has KunMingHu's RTl been finalized (IIRC, we have developing vector unit)? And can we have different doc for different generations of XiangShan? https://github.com/llvm/llvm-project/pull/89359 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
@@ -7238,10 +7238,15 @@ void Clang::ConstructJob(Compilation , const
JobAction ,
Args.addOptInFlag(CmdArgs, options::OPT_frelaxed_template_template_args,
options::OPT_fno_relaxed_template_template_args);
- // -fsized-deallocation is off by default, as it is an ABI-breaking change
for
- // most platforms.
- Args.addOptInFlag(CmdArgs, options::OPT_fsized_deallocation,
-options::OPT_fno_sized_deallocation);
+ // -fsized-deallocation is on by default in C++14 onwards and otherwise off
+ // by default.
+ if (Arg *A = Args.getLastArg(options::OPT_fsized_deallocation,
+ options::OPT_fno_sized_deallocation)) {
+if (A->getOption().matches(options::OPT_fno_sized_deallocation))
+ CmdArgs.push_back("-fno-sized-deallocation");
wangpc-pp wrote:
Sorry for bothering you, but I'd like to know if it makes sense to you.
@MaskRay
https://github.com/llvm/llvm-project/pull/83774
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[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)
wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q?itial=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.4 --- clang/test/Driver/riscv-cpus.c| 319 ++ clang/test/Misc/target-invalid-cpu-note.c | 8 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 224 ++- 3 files changed, 539 insertions(+), 12 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index ff2bd6f7c8ba34..a285f0f9c41f54 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -302,3 +302,322 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// Check profile CPUs + +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s +// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s +// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s +// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+m" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+a" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+f" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+d" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+c" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s +// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare" +// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s +// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature"
[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)
https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/88474 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)
wangpc-pp wrote: > Can you add it to RVA23 profile? > > https://github.com/llvm/llvm-project/blob/f71e25bb669d662f98823d6d81b3f918538c9239/llvm/lib/Support/RISCVISAInfo.cpp#L250-L284 Never mind, it's an optional extension. https://github.com/llvm/llvm-project/pull/88474 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)
wangpc-pp wrote: Can you add it to RVA23 profile? https://github.com/llvm/llvm-project/blob/f71e25bb669d662f98823d6d81b3f918538c9239/llvm/lib/Support/RISCVISAInfo.cpp#L250-L284 https://github.com/llvm/llvm-project/pull/88474 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)
@@ -704,6 +705,12 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
// CHECK-ZACAS-EXT: __riscv_zacas 100{{$}}
+// RUN: %clang --target=riscv32 -march=rv32izama16b -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZAMA16B-EXT %s
wangpc-pp wrote:
We need to indent 2 spaces here.
https://github.com/llvm/llvm-project/pull/88474
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[clang] [llvm] [RISCV] Add B extension (PR #76893)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76893
>From 169ef33f585b964d9af7a7628919271245f318fc Mon Sep 17 00:00:00 2001
From: wangpc
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH 1/3] [RISCV] Add B extension
It seems that we have `B` extension again: https://github.com/riscv/riscv-b
According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
clang/test/Driver/riscv-arch.c | 5 -
clang/test/Preprocessor/riscv-target-features.c | 12
llvm/docs/RISCVUsage.rst| 1 +
llvm/lib/Support/RISCVISAInfo.cpp | 3 +++
llvm/lib/Target/RISCV/RISCVFeatures.td | 8
llvm/test/CodeGen/RISCV/attributes.ll | 4
llvm/unittests/Support/RISCVISAInfoTest.cpp | 6 ++
7 files changed, 30 insertions(+), 9 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 8399b4e97f86d5..8e48ed9160992d 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
// RV32-STD: error: invalid arch name 'rv32imqc',
// RV32-STD: unsupported standard user-level extension 'q'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
// RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index ec7764bb538189..dfdef72cb1e755 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
// CHECK-NOT: __riscv_64e {{.*$}}
// CHECK-NOT: __riscv_a {{.*$}}
// CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
// CHECK-NOT: __riscv_c {{.*$}}
// CHECK-NOT: __riscv_compressed {{.*$}}
// CHECK-NOT: __riscv_d {{.*$}}
@@ -191,6 +192,17 @@
// CHECK-A-EXT: __riscv_a 2001000{{$}}
// CHECK-A-EXT: __riscv_atomic 1
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ic -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 6f5eba263def43..232604788f9972 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
Extension Status
=
``A`` Supported
+ ``B`` Supported
``C`` Supported
``D`` Supported
``F`` Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 7a19d24d1ff483..99962501153b0e 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -52,6 +52,7 @@ static const char *RISCVGImplications[] = {
// NOTE: This table should be sorted alphabetically by extension name.
static const RISCVSupportedExtension SupportedExtensions[] = {
{"a", {2, 1}},
+{"b", {1, 0}},
{"c", {2, 0}},
{"d", {2, 2}},
{"e", {2, 0}},
@@ -1106,6 +1107,7 @@ Error RISCVISAInfo::checkDependency() {
return Error::success();
}
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
static const char *ImpliedExtsD[] = {"f"};
static const char *ImpliedExtsF[] = {"zicsr"};
static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1181,6 +1183,7 @@ struct ImpliedExtsEntry {
// Note: The table needs to be sorted by name.
static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
{{"d"}, {ImpliedExtsD}},
{{"f"}, {ImpliedExtsF}},
{{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 794455aa730400..33541be37537df 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -430,6 +430,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
// Bitmanip Extensions for Cryptography Extensions
+def FeatureStdExtB
+: SubtargetFeature<"b", "HasStdExtB", "true",
+ "'B' (the collection of the Zba, Zbb, Zbs
[clang] [llvm] [RISCV] Add B extension (PR #76893)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76893
>From 169ef33f585b964d9af7a7628919271245f318fc Mon Sep 17 00:00:00 2001
From: wangpc
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH 1/2] [RISCV] Add B extension
It seems that we have `B` extension again: https://github.com/riscv/riscv-b
According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
clang/test/Driver/riscv-arch.c | 5 -
clang/test/Preprocessor/riscv-target-features.c | 12
llvm/docs/RISCVUsage.rst| 1 +
llvm/lib/Support/RISCVISAInfo.cpp | 3 +++
llvm/lib/Target/RISCV/RISCVFeatures.td | 8
llvm/test/CodeGen/RISCV/attributes.ll | 4
llvm/unittests/Support/RISCVISAInfoTest.cpp | 6 ++
7 files changed, 30 insertions(+), 9 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 8399b4e97f86d5..8e48ed9160992d 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
// RV32-STD: error: invalid arch name 'rv32imqc',
// RV32-STD: unsupported standard user-level extension 'q'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
// RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index ec7764bb538189..dfdef72cb1e755 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
// CHECK-NOT: __riscv_64e {{.*$}}
// CHECK-NOT: __riscv_a {{.*$}}
// CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
// CHECK-NOT: __riscv_c {{.*$}}
// CHECK-NOT: __riscv_compressed {{.*$}}
// CHECK-NOT: __riscv_d {{.*$}}
@@ -191,6 +192,17 @@
// CHECK-A-EXT: __riscv_a 2001000{{$}}
// CHECK-A-EXT: __riscv_atomic 1
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ic -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 6f5eba263def43..232604788f9972 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
Extension Status
=
``A`` Supported
+ ``B`` Supported
``C`` Supported
``D`` Supported
``F`` Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 7a19d24d1ff483..99962501153b0e 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -52,6 +52,7 @@ static const char *RISCVGImplications[] = {
// NOTE: This table should be sorted alphabetically by extension name.
static const RISCVSupportedExtension SupportedExtensions[] = {
{"a", {2, 1}},
+{"b", {1, 0}},
{"c", {2, 0}},
{"d", {2, 2}},
{"e", {2, 0}},
@@ -1106,6 +1107,7 @@ Error RISCVISAInfo::checkDependency() {
return Error::success();
}
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
static const char *ImpliedExtsD[] = {"f"};
static const char *ImpliedExtsF[] = {"zicsr"};
static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1181,6 +1183,7 @@ struct ImpliedExtsEntry {
// Note: The table needs to be sorted by name.
static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
{{"d"}, {ImpliedExtsD}},
{{"f"}, {ImpliedExtsF}},
{{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 794455aa730400..33541be37537df 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -430,6 +430,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
// Bitmanip Extensions for Cryptography Extensions
+def FeatureStdExtB
+: SubtargetFeature<"b", "HasStdExtB", "true",
+ "'B' (the collection of the Zba, Zbb, Zbs
[clang] [llvm] [RISCV] Add B extension (PR #76893)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76893
>From 169ef33f585b964d9af7a7628919271245f318fc Mon Sep 17 00:00:00 2001
From: wangpc
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension
It seems that we have `B` extension again: https://github.com/riscv/riscv-b
According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
clang/test/Driver/riscv-arch.c | 5 -
clang/test/Preprocessor/riscv-target-features.c | 12
llvm/docs/RISCVUsage.rst| 1 +
llvm/lib/Support/RISCVISAInfo.cpp | 3 +++
llvm/lib/Target/RISCV/RISCVFeatures.td | 8
llvm/test/CodeGen/RISCV/attributes.ll | 4
llvm/unittests/Support/RISCVISAInfoTest.cpp | 6 ++
7 files changed, 30 insertions(+), 9 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 8399b4e97f86d5..8e48ed9160992d 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
// RV32-STD: error: invalid arch name 'rv32imqc',
// RV32-STD: unsupported standard user-level extension 'q'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
// RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index ec7764bb538189..dfdef72cb1e755 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
// CHECK-NOT: __riscv_64e {{.*$}}
// CHECK-NOT: __riscv_a {{.*$}}
// CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
// CHECK-NOT: __riscv_c {{.*$}}
// CHECK-NOT: __riscv_compressed {{.*$}}
// CHECK-NOT: __riscv_d {{.*$}}
@@ -191,6 +192,17 @@
// CHECK-A-EXT: __riscv_a 2001000{{$}}
// CHECK-A-EXT: __riscv_atomic 1
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ic -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 6f5eba263def43..232604788f9972 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
Extension Status
=
``A`` Supported
+ ``B`` Supported
``C`` Supported
``D`` Supported
``F`` Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 7a19d24d1ff483..99962501153b0e 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -52,6 +52,7 @@ static const char *RISCVGImplications[] = {
// NOTE: This table should be sorted alphabetically by extension name.
static const RISCVSupportedExtension SupportedExtensions[] = {
{"a", {2, 1}},
+{"b", {1, 0}},
{"c", {2, 0}},
{"d", {2, 2}},
{"e", {2, 0}},
@@ -1106,6 +1107,7 @@ Error RISCVISAInfo::checkDependency() {
return Error::success();
}
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
static const char *ImpliedExtsD[] = {"f"};
static const char *ImpliedExtsF[] = {"zicsr"};
static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1181,6 +1183,7 @@ struct ImpliedExtsEntry {
// Note: The table needs to be sorted by name.
static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
{{"d"}, {ImpliedExtsD}},
{{"f"}, {ImpliedExtsF}},
{{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 794455aa730400..33541be37537df 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -430,6 +430,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
// Bitmanip Extensions for Cryptography Extensions
+def FeatureStdExtB
+: SubtargetFeature<"b", "HasStdExtB", "true",
+ "'B' (the collection of the Zba, Zbb, Zbs
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From 1e556e00e59377c76c168293d6c2678f7a874742 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/2] [clang] Enable sized deallocation by default in C++14
onwards
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
Differential Revision: https://reviews.llvm.org/D112921
---
.../clangd/unittests/FindTargetTests.cpp | 4 +-
.../checkers/misc/new-delete-overloads.cpp| 10 -
clang/docs/ReleaseNotes.rst | 5 +
clang/include/clang/Driver/Options.td | 7 +-
clang/lib/Driver/ToolChains/Clang.cpp | 13 +-
clang/lib/Driver/ToolChains/Darwin.cpp| 58 -
clang/lib/Driver/ToolChains/Darwin.h | 4 +
clang/lib/Driver/ToolChains/ZOS.cpp | 6 +
clang/test/AST/ast-dump-expr-json.cpp | 2 +-
clang/test/AST/ast-dump-expr.cpp | 2 +-
clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +-
.../basic.stc.dynamic.deallocation/p2.cpp | 2 +-
clang/test/CXX/drs/dr292.cpp | 17 +-
.../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +-
.../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +-
.../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +-
.../CodeGenCXX/cxx2a-destroying-delete.cpp| 4 +-
clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +-
clang/test/CodeGenCXX/delete.cpp | 12 +-
clang/test/CodeGenCXX/dllimport.cpp | 4 +-
clang/test/CodeGenCXX/new.cpp | 6 +-
.../coro-aligned-alloc-2.cpp | 2 -
.../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 -
clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +-
clang/test/CodeGenCoroutines/pr56919.cpp | 9 +-
clang/test/Lexer/cxx-features.cpp | 20 +-
clang/test/PCH/cxx1z-aligned-alloc.cpp| 10 +-
clang/test/SemaCXX/MicrosoftExtensions.cpp| 8 +-
.../SemaCXX/builtin-operator-new-delete.cpp | 2 +-
.../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +-
.../unavailable_aligned_allocation.cpp| 15 +-
clang/tools/clang-repl/CMakeLists.txt | 59 +
clang/unittests/Interpreter/CMakeLists.txt| 59 +
.../StaticAnalyzer/CallEventTest.cpp | 2 +-
clang/www/cxx_status.html | 11 +-
.../support.dynamic/libcpp_deallocate.sh.cpp | 3 +
.../sized_delete_array14.pass.cpp | 8 +-
.../new.delete.single/sized_delete14.pass.cpp | 8 +-
42 files changed, 555 insertions(+), 112 deletions(-)
diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 0af6036734ba53..1b7b96281dfaa5 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
[[delete]] x;
}
)cpp";
- EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+ // Sized deallocation is enabled by default in C++14 onwards.
+ EXPECT_DECLS("CXXDeleteExpr",
+ "void operator delete(void *, unsigned long) noexcept");
}
TEST_F(TargetDeclTest, DependentExprs) {
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e19..f86fe8a4c5b14f 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
// CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has
no matching declaration of 'operator delete' at the same scope
void *operator new(size_t size) noexcept(false);
-struct T {
- // Sized deallocations are not enabled by default, and so this new/delete
pair
- // does not match. However, we expect only one warning, for the new, because
- // the operator delete is a placement delete and we do not warn on
mismatching
- // placement operations.
- // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new'
has no matching declaration of 'operator delete' at the same scope
- void *operator new(size_t size) noexcept;
- void operator delete(void *ptr, size_t) noexcept; // ok only if sized
deallocation is enabled
-};
-
struct U {
void *operator new(size_t size) noexcept;
void operator delete(void *ptr) noexcept;
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
@@ -7238,10 +7238,15 @@ void Clang::ConstructJob(Compilation , const
JobAction ,
Args.addOptInFlag(CmdArgs, options::OPT_frelaxed_template_template_args,
options::OPT_fno_relaxed_template_template_args);
- // -fsized-deallocation is off by default, as it is an ABI-breaking change
for
- // most platforms.
- Args.addOptInFlag(CmdArgs, options::OPT_fsized_deallocation,
-options::OPT_fno_sized_deallocation);
+ // -fsized-deallocation is on by default in C++14 onwards and otherwise off
+ // by default.
+ if (Arg *A = Args.getLastArg(options::OPT_fsized_deallocation,
+ options::OPT_fno_sized_deallocation)) {
+if (A->getOption().matches(options::OPT_fno_sized_deallocation))
+ CmdArgs.push_back("-fno-sized-deallocation");
wangpc-pp wrote:
I don't know if I understand correctly, but I think we need both clang and cc1
options for `sized_deallocation`. Please see `aligned_allocation` case, which
is the same as `sized_deallocation`:
https://github.com/llvm/llvm-project/blob/24e8c6a09b7d226dbe706aeae7aebf479a1e5087/clang/include/clang/Driver/Options.td#L3355-L3358
And there are a lot of tests assumed we have cc1 options
`-fno-sized-deallocation` and `-fsized-deallocation` like
[`clang/test/SemaCXX/builtin-operator-new-delete.cpp`](https://github.com/llvm/llvm-project/blob/main/clang/test/SemaCXX/builtin-operator-new-delete.cpp).
https://github.com/llvm/llvm-project/pull/83774
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[clang] [llvm] [RISCV] Zimop/Zcmop are ratified (PR #87966)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/87966 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Zimop/Zcmop are ratified (PR #87966)
https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/87966 Remove them from experimental. See also: https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc >From 5b312a80cdc3396e3e35d906176f56349392d437 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Mon, 8 Apr 2024 15:33:19 +0800 Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?= =?UTF-8?q?l=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.6-beta.1 --- clang/test/Driver/riscv-profiles.c| 26 +++--- .../test/Preprocessor/riscv-target-features.c | 36 +-- llvm/docs/RISCVUsage.rst | 6 llvm/lib/Support/RISCVISAInfo.cpp | 26 +++--- llvm/lib/Target/RISCV/RISCVFeatures.td| 4 +-- llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td | 2 -- llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td | 2 -- llvm/test/CodeGen/RISCV/attributes.ll | 16 - .../test/CodeGen/RISCV/rv32zimop-intrinsic.ll | 2 +- .../test/CodeGen/RISCV/rv64zimop-intrinsic.ll | 2 +- llvm/test/MC/RISCV/attribute-arch.s | 2 +- llvm/test/MC/RISCV/compressed-zicfiss.s | 12 +++ llvm/test/MC/RISCV/rv32zcmop-invalid.s| 2 +- llvm/test/MC/RISCV/rv32zimop-invalid.s| 2 +- llvm/test/MC/RISCV/rvzcmop-valid.s| 12 +++ llvm/test/MC/RISCV/rvzimop-valid.s| 12 +++ llvm/unittests/Support/RISCVISAInfoTest.cpp | 4 +-- 17 files changed, 78 insertions(+), 90 deletions(-) diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c index ec9206f2f45370..647567d4c971f4 100644 --- a/clang/test/Driver/riscv-profiles.c +++ b/clang/test/Driver/riscv-profiles.c @@ -111,7 +111,7 @@ // RVA22S64: "-target-feature" "+svinval" // RVA22S64: "-target-feature" "+svpbmt" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 \ // RUN: | FileCheck -check-prefix=RVA23U64 %s // RVA23U64: "-target-feature" "+m" // RVA23U64: "-target-feature" "+a" @@ -133,13 +133,13 @@ // RVA23U64: "-target-feature" "+zihintntl" // RVA23U64: "-target-feature" "+zihintpause" // RVA23U64: "-target-feature" "+zihpm" -// RVA23U64: "-target-feature" "+experimental-zimop" +// RVA23U64: "-target-feature" "+zimop" // RVA23U64: "-target-feature" "+za64rs" // RVA23U64: "-target-feature" "+zawrs" // RVA23U64: "-target-feature" "+zfa" // RVA23U64: "-target-feature" "+zfhmin" // RVA23U64: "-target-feature" "+zcb" -// RVA23U64: "-target-feature" "+experimental-zcmop" +// RVA23U64: "-target-feature" "+zcmop" // RVA23U64: "-target-feature" "+zba" // RVA23U64: "-target-feature" "+zbb" // RVA23U64: "-target-feature" "+zbs" @@ -172,13 +172,13 @@ // RVA23S64: "-target-feature" "+zihintntl" // RVA23S64: "-target-feature" "+zihintpause" // RVA23S64: "-target-feature" "+zihpm" -// RVA23S64: "-target-feature" "+experimental-zimop" +// RVA23S64: "-target-feature" "+zimop" // RVA23S64: "-target-feature" "+za64rs" // RVA23S64: "-target-feature" "+zawrs" // RVA23S64: "-target-feature" "+zfa" // RVA23S64: "-target-feature" "+zfhmin" // RVA23S64: "-target-feature" "+zcb" -// RVA23S64: "-target-feature" "+experimental-zcmop" +// RVA23S64: "-target-feature" "+zcmop" // RVA23S64: "-target-feature" "+zba" // RVA23S64: "-target-feature" "+zbb" // RVA23S64: "-target-feature" "+zbs" @@ -207,7 +207,7 @@ // RVA23S64: "-target-feature" "+svnapot" // RVA23S64: "-target-feature" "+svpbmt" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23u64 -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23u64 \ // RUN: | FileCheck -check-prefix=RVB23U64 %s // RVB23U64: "-target-feature" "+m" // RVB23U64: "-target-feature" "+a" @@ -228,12 +228,12 @@ // RVB23U64: "-target-feature" "+zihintntl" // RVB23U64: "-target-feature" "+zihintpause" // RVB23U64: "-target-feature" "+zihpm" -// RVB23U64: "-target-feature" "+experimental-zimop" +// RVB23U64: "-target-feature" "+zimop" // RVB23U64: "-target-feature" "+za64rs" // RVB23U64: "-target-feature" "+zawrs" // RVB23U64: "-target-feature" "+zfa" // RVB23U64: "-target-feature" "+zcb" -// RVB23U64: "-target-feature" "+experimental-zcmop" +// RVB23U64: "-target-feature" "+zcmop" // RVB23U64: "-target-feature" "+zba" // RVB23U64: "-target-feature" "+zbb" // RVB23U64: "-target-feature" "+zbs" @@ -261,12 +261,12 @@ // RVB23S64: "-target-feature" "+zihintntl" // RVB23S64: "-target-feature" "+zihintpause" // RVB23S64: "-target-feature" "+zihpm" -// RVB23S64: "-target-feature" "+experimental-zimop" +// RVB23S64: "-target-feature" "+zimop" // RVB23S64: "-target-feature" "+za64rs" // RVB23S64: "-target-feature" "+zawrs" // RVB23S64: "-target-feature" "+zfa" // RVB23S64: "-target-feature" "+zcb" -//
