[coreboot] [PATCH] Changes for DLP 1232H external programer to Flashrom
Hi all.
These are the changes I had to do the flashrom to get my in circuit
programer working. Not much as you can see.
Unfortunately it seems to have problems writing to the chip. The first
time I tried it it worked well. Writing random data to the chip. But
when I then tried to write the bios image. After several tries, adding
more capacitors, increasing the bus speed (yes increasing not
decreasing) and always erasing the chip before doing a write I got
good write. There where a couple of write runs that seems to be get
partial success, parts of the bios looked okay while parts where still
all FF. Increasing the bus speed seemed to make it write more data.
I have some pictures of the programer here:
http://irc.walkyrie.se/coreboot/pictures/
Signed-off-by: Jakob Bornecrantz wallbra...@gmail.com
Cheers Jakob.
Index: ft2232_spi.c
===
--- ft2232_spi.c (revision 632)
+++ ft2232_spi.c (working copy)
@@ -29,6 +29,14 @@
#include ftdi.h
+/* Select chip to connect to, exactly one must be set */
+#define USE_FT2232 1
+#define USE_FT4232 0
+
+/* Select interface to use, exactly one must be set.*/
+#define USE_INTERFACE_A 1
+#define USE_INTERFACE_B 0
+
/* the 'H' chips can run internally at either 12Mhz or 60Mhz.
* the non-H chips can only run at 12Mhz. */
#define CLOCK_5X 1
@@ -78,8 +86,13 @@
return EXIT_FAILURE;
}
- // f = ftdi_usb_open(ftdic, 0x0403, 0x6010); // FT2232
+#if USE_FT2232
+ f = ftdi_usb_open(ftdic, 0x0403, 0x6010); // FT2232
+#elif USE_FT4232
f = ftdi_usb_open(ftdic, 0x0403, 0x6011); // FT4232
+#else
+#error Select either FT2232 or FT4232
+#endif
if (f 0 f != -5) {
fprintf(stderr, Unable to open ftdi device: %d (%s)\n, f,
@@ -87,10 +100,19 @@
exit(-1);
}
+#if USE_INTERFACE_A
+ if (ftdi_set_interface(ftdic, INTERFACE_A) 0) {
+ fprintf(stderr, Unable to select FT2232 channel A: %s\n,
+ftdic-error_str);
+ }
+#elif USE_INTERFACE_B
if (ftdi_set_interface(ftdic, INTERFACE_B) 0) {
fprintf(stderr, Unable to select FT2232 channel B: %s\n,
ftdic-error_str);
}
+#else
+#error Select either interface A or B
+#endif
if (ftdi_usb_reset(ftdic) 0) {
fprintf(stderr, Unable to reset ftdi device\n);
--
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Re: [coreboot] [PATCH] SB600 suspend/S3 try
Hi,
I'm attaching version which has all missing stuff but I cannot get it to
compile. I changed the ACPI init to early and also it moves the FADT to SB600 dir.
Please try to fix the patch.
Rudolf
Index: src/southbridge/amd/sb600/sb600.h
===
--- src/southbridge/amd/sb600/sb600.h (revision 4369)
+++ src/southbridge/amd/sb600/sb600.h (working copy)
@@ -24,11 +24,22 @@
#include chip.h
/* Power management index/data registers */
+#define BIOSRAM_INDEX 0xcd4
+#define BIOSRAM_DATA 0xcd5
#define PM_INDEX 0xcd6
#define PM_DATA 0xcd7
#define PM2_INDEX 0xcd0
#define PM2_DATA 0xcd1
+#define SB600_PM_BASE 0x800
+
+#define ACPI_PM_EVT_BLK (SB600_PM_BASE + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK (SB600_PM_BASE + 0x04) /* 2 bytes */
+#define ACPI_PMA_CNT_BLK (SB600_PM_BASE + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK (SB600_PM_BASE + 0x18) /* 4 bytes */
+#define ACPI_GPE0_BLK (SB600_PM_BASE + 0x10) /* 8 bytes */
+#define ACPI_CPU_CONTORL (SB600_PM_BASE + 0x08) /* 6 bytes */
+
extern void pm_iowrite(u8 reg, u8 value);
extern u8 pm_ioread(u8 reg);
extern void pm2_iowrite(u8 reg, u8 value);
Index: src/southbridge/amd/sb600/sb600_early_setup.c
===
--- src/southbridge/amd/sb600/sb600_early_setup.c (revision 4369)
+++ src/southbridge/amd/sb600/sb600_early_setup.c (working copy)
@@ -23,15 +23,15 @@
#define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */
/*SIZE 0x40 */
+#define S3_NVRAM_EARLY 1
-
-static void pmio_write(u8 reg, u8 value)
+void pmio_write(u8 reg, u8 value)
{
outb(reg, PM_INDEX);
outb(value, PM_INDEX + 1);
}
-static u8 pmio_read(u8 reg)
+u8 pmio_read(u8 reg)
{
outb(reg, PM_INDEX);
return inb(PM_INDEX + 1);
@@ -667,6 +667,34 @@
sb600_pci_cfg();
}
+static void sb600_acpi_init(void) {
+ pm_iowrite(0x20, ACPI_PM_EVT_BLK 0xFF);
+ pm_iowrite(0x21, ACPI_PM_EVT_BLK 8);
+ pm_iowrite(0x22, ACPI_PM1_CNT_BLK 0xFF);
+ pm_iowrite(0x23, ACPI_PM1_CNT_BLK 8);
+ pm_iowrite(0x24, ACPI_PM_TMR_BLK 0xFF);
+ pm_iowrite(0x25, ACPI_PM_TMR_BLK 8);
+ pm_iowrite(0x28, ACPI_GPE0_BLK 0xFF);
+ pm_iowrite(0x29, ACPI_GPE0_BLK 8);
+
+ /* CpuControl is in \_PR.CPU0, 6 bytes */
+ pm_iowrite(0x26, ACPI_CPU_CONTORL 0xFF);
+ pm_iowrite(0x27, ACPI_CPU_CONTORL 8);
+
+ pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
+ pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
+
+ pm_iowrite(0x2C, ACPI_PMA_CNT_BLK 0xFF);
+ pm_iowrite(0x2D, ACPI_PMA_CNT_BLK 8);
+
+ pm_iowrite(0x0E, 13 | 02); /* AcpiDecodeEnable, When set, SB uses
+ * the contents of the PM registers at
+ * index 20-2B to decode ACPI I/O address.
+ * AcpiSmiEn SmiCmdEn*/
+ pm_iowrite(0x10, 11 | 13| 15); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
+}
+
/*
* This function should be called after enable_sb600_smbus().
*/
@@ -674,6 +702,7 @@
{
printk_info(sb600_early_setup()\n);
sb600_por_init();
+ sb600_acpi_init();
}
static int smbus_read_byte(u32 device, u32 address)
@@ -681,3 +710,42 @@
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
+int s3_save_nvram_early(u32 dword, int size, int nvram_pos) {
+ int i;
+ printk_debug(Writing %x of size %d to nvram pos: %d\n, dword, size, nvram_pos);
+
+ for (i = 0; isize; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ outb((dword (8 * i)) 0xff , BIOSRAM_DATA);
+ nvram_pos++;
+ }
+
+ return nvram_pos;
+}
+
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
+ u32 data = *old_dword;
+ int i;
+ for (i = 0; isize; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ data = ~(0xff (i * 8));
+ data |= inb(BIOSRAM_DATA) (i *8);
+ nvram_pos++;
+ }
+ *old_dword = data;
+ printk_debug(Loading %x of size %d to nvram pos:%d\n, * old_dword, size, nvram_pos-size);
+ return nvram_pos;
+}
+
+#define ACPI_IS_WAKEUP_EARLY 1
+
+int acpi_is_wakeup_early(void) {
+ device_t dev;
+ u16 tmp;
+
+ print_debug(IN TEST WAKEUP\n);
+ tmp = inw(ACPI_PM1_CNT_BLK);
+ print_debug_hex8(tmp);
+ return ((tmp (7 10)) 10) == 1 ? 3 : 0 ;
+}
+
Index: src/southbridge/amd/sb600/Config.lb
===
--- src/southbridge/amd/sb600/Config.lb (revision 4369)
+++ src/southbridge/amd/sb600/Config.lb (working copy)
@@ -19,6 +19,8 @@
##
##
+uses HAVE_ACPI_TABLES
+
config chip.h
driver sb600.o
driver sb600_usb.o
@@ -30,5 +32,7 @@
driver sb600_ac97.o
driver sb600_pci.o
object sb600_reset.o
+if HAVE_ACPI_TABLES
+ object sb600_fadt.o
+end
-
Index: src/southbridge/amd/sb600/sb600_fadt.c
===
--- src/southbridge/amd/sb600/sb600_fadt.c (revision 0)
+++ src/southbridge/amd/sb600/sb600_fadt.c (revision 0)
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it
Re: [coreboot] User:Hailfinger/Drafts/Women
Just worth noting: the cofounder of the LinuxBIOS project, from which this all began in 1999, was Sung-Eun Choi: http://www.coreboot.org/File:For_scale.jpg She created our original logo and web page, wrote code, wrote papers, got us to conferences, and did a lot of other work. She is an accomplished CS researcher in her own right and now works at Cray. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] Handle programmer init errors, fix IT87* SPI init
Handle programmer init errors and abort. If the programmer didn't
initialize correctly, it is pointless to continue.
Fix standalone IT87* SPI init to set flashbus to NONE if no IT87* SPI
communication is possible.
Print the I/O port detected by the IT87* SPI code.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-programmer_init_errorcheck_it87spi_initfix/it87spi.c
===
--- flashrom-programmer_init_errorcheck_it87spi_initfix/it87spi.c
(Revision 632)
+++ flashrom-programmer_init_errorcheck_it87spi_initfix/it87spi.c
(Arbeitskopie)
@@ -83,11 +83,12 @@
tmp |= 1 4;
sio_write(port, 0x24, tmp);
}
- printf(serial flash pin %i\n, (tmp 1 5) ? 87 : 29);
+ printf(Serial flash pin %i\n, (tmp 1 5) ? 87 : 29);
/* LDN 0x7, reg 0x64/0x65 */
sio_write(port, 0x07, 0x7);
flashport = sio_read(port, 0x64) 8;
flashport |= sio_read(port, 0x65);
+ printf(Serial flash port 0x%04x\n, flashport);
}
exit_conf_mode_ite(port);
return flashport;
@@ -113,8 +114,11 @@
get_io_perms();
ret = it87spi_common_init();
- if (!ret)
+ if (!ret) {
buses_supported = CHIP_BUSTYPE_SPI;
+ } else {
+ buses_supported = CHIP_BUSTYPE_NONE;
+ }
return ret;
}
Index: flashrom-programmer_init_errorcheck_it87spi_initfix/flashrom.c
===
--- flashrom-programmer_init_errorcheck_it87spi_initfix/flashrom.c
(Revision 632)
+++ flashrom-programmer_init_errorcheck_it87spi_initfix/flashrom.c
(Arbeitskopie)
@@ -692,7 +692,10 @@
if (optind argc)
filename = argv[optind++];
- ret = programmer_init();
+ if (programmer_init()) {
+ fprintf(stderr, Error: Programmer initialization failed.\n);
+ exit(1);
+ }
myusec_calibrate_delay();
--
http://www.hailfinger.org/
Index: flashrom-programmer_init_errorcheck_it87spi_initfix/it87spi.c
===
--- flashrom-programmer_init_errorcheck_it87spi_initfix/it87spi.c
(Revision 632)
+++ flashrom-programmer_init_errorcheck_it87spi_initfix/it87spi.c
(Arbeitskopie)
@@ -83,11 +83,12 @@
tmp |= 1 4;
sio_write(port, 0x24, tmp);
}
- printf(serial flash pin %i\n, (tmp 1 5) ? 87 : 29);
+ printf(Serial flash pin %i\n, (tmp 1 5) ? 87 : 29);
/* LDN 0x7, reg 0x64/0x65 */
sio_write(port, 0x07, 0x7);
flashport = sio_read(port, 0x64) 8;
flashport |= sio_read(port, 0x65);
+ printf(Serial flash port 0x%04x\n, flashport);
}
exit_conf_mode_ite(port);
return flashport;
@@ -113,8 +114,11 @@
get_io_perms();
ret = it87spi_common_init();
- if (!ret)
+ if (!ret) {
buses_supported = CHIP_BUSTYPE_SPI;
+ } else {
+ buses_supported = CHIP_BUSTYPE_NONE;
+ }
return ret;
}
Index: flashrom-programmer_init_errorcheck_it87spi_initfix/flashrom.c
===
--- flashrom-programmer_init_errorcheck_it87spi_initfix/flashrom.c
(Revision 632)
+++ flashrom-programmer_init_errorcheck_it87spi_initfix/flashrom.c
(Arbeitskopie)
@@ -692,7 +692,10 @@
if (optind argc)
filename = argv[optind++];
- ret = programmer_init();
+ if (programmer_init()) {
+ fprintf(stderr, Error: Programmer initialization failed.\n);
+ exit(1);
+ }
myusec_calibrate_delay();
--
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[coreboot] [RFC] killing the old flashrom tree
Hi, it seems some people still try to check out the old flashrom repo. That code is not only ancient, it also lacks some fixes we have in newer code. I have the following two suggested options for deletion: 1. Remove the whole directory. 2. Remove all files in the directory and just keep the file which says the repo moved. Opinions? Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Handle programmer init errors, fix IT87* SPI init
On Sat, Jun 27, 2009 at 02:54:30PM +0200, Carl-Daniel Hailfinger wrote: Handle programmer init errors and abort. If the programmer didn't initialize correctly, it is pointless to continue. Fix standalone IT87* SPI init to set flashbus to NONE if no IT87* SPI communication is possible. Print the I/O port detected by the IT87* SPI code. Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net Acked-by: Ward Vandewege w...@gnu.org Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [RFC] killing the old flashrom tree
On Sat, Jun 27, 2009 at 03:02:33PM +0200, Carl-Daniel Hailfinger wrote: it seems some people still try to check out the old flashrom repo. That That would be me, working from old flashrom checkouts :/ code is not only ancient, it also lacks some fixes we have in newer code. I have the following two suggested options for deletion: 1. Remove the whole directory. 2. Remove all files in the directory and just keep the file which says the repo moved. Option 1 is probably best - I'd prefer it to error out in an obvious way. Svn wouldn't be able to follow a http redirect would it? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] User:Hailfinger/Drafts/Women
On Sat, 27 Jun 2009 05:01:41 -0700, ron minnich rminn...@gmail.com wrote: Just worth noting: the cofounder of the LinuxBIOS project, from which this all began in 1999, was Sung-Eun Choi: http://www.coreboot.org/File:For_scale.jpg She created our original logo and web page, wrote code, wrote papers, got us to conferences, and did a lot of other work. She is an accomplished CS researcher in her own right and now works at Cray. Now something like that may be worth mentioning on the Wiki. That's the kind of stuff we all can aspire for! :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4376 - in trunk/coreboot-v2/targets/via: . epia-m700
Author: uwe Date: 2009-06-27 18:06:51 +0200 (Sat, 27 Jun 2009) New Revision: 4376 Added: trunk/coreboot-v2/targets/via/epia-m700/ trunk/coreboot-v2/targets/via/epia-m700/Config.lb Log: Add a target/ directory for the VIA EPIA-M700 board, so we can build it. Note that this board is nowhere near usable, further patches will follow and hopefully get this into buildable and usable shape. Signed-off-by: Uwe Hermann u...@hermann-uwe.de Acked-by: Uwe Hermann u...@hermann-uwe.de Added: trunk/coreboot-v2/targets/via/epia-m700/Config.lb === --- trunk/coreboot-v2/targets/via/epia-m700/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/via/epia-m700/Config.lb 2009-06-27 16:06:51 UTC (rev 4376) @@ -0,0 +1,29 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann u...@hermann-uwe.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target epia-m700 +mainboard via/epia-m700 + +romimage image + option COREBOOT_EXTRA_VERSION = -epia-m700 + payload ../payload.elf +end + +buildrom ./coreboot.rom ROM_SIZE image -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4376
Dear coreboot readers! This is the automatic build system of coreboot. The developer uwe checked in revision 4376 to the coreboot repository. This caused the following changes: Change Log: Add a target/ directory for the VIA EPIA-M700 board, so we can build it. Note that this board is nowhere near usable, further patches will follow and hopefully get this into buildable and usable shape. Signed-off-by: Uwe Hermann u...@hermann-uwe.de Acked-by: Uwe Hermann u...@hermann-uwe.de Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4376device=sandpointx3_altimus_mpc7410vendor=motorolanum=2 Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4376device=epia-m700vendor=vianum=2 If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Missing entry16.inc for vx800
Here are the two missing entry16 files for the vx800. -Bari /* This software and ancillary information (herein called SOFTWARE ) called LinuxBIOS is made available under the terms described here. The SOFTWARE has been approved for release with associated LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has been authored by an employee or employees of the University of California, operator of the Los Alamos National Laboratory under Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The U.S. Government has rights to use, reproduce, and distribute this SOFTWARE. The public may copy, distribute, prepare derivative works and publicly display this SOFTWARE without charge, provided that this Notice and any statement of authorship are reproduced on all copies. Neither the Government nor the University makes any warranty, express or implied, or assumes any liability or responsibility for the use of this SOFTWARE. If SOFTWARE is modified to produce derivative works, such modified SOFTWARE should be clearly marked, so as not to confuse it with the version available from LANL. */ /* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL * rminn...@lanl.gov */ /** Start code to put an i386 or later processor into 32-bit * protected mode. */ /* .section .rom.text */ #include arch/rom_segs.h .code16 .globl _start .type _start, @function _start: cli /* Save the BIST result */ movl%eax, %ebp /* 2008-12-2 added this--*/ /*Open A20 */ /*inb $0x92, %al orb $0x2,%al outb %al, $0x92*/ /*;--; ;Disable NMI and PARITY; ;--; */ /*movb $0x8d,%al*/ /*; disable parity*/ /*outb %al, $0x70 movb$0xc,%al */ /*; disable NMI*/ /*outb %al, $0x61*/ /* 2008-12-2 added this-*/ /* thanks to km...@sis.tw.com for this TBL fix ... */ /**/ /* IMMEDIATELY invalidate the translation lookaside buffer before executing*/ /* any further code. Even though paging is disabled we could still get*/ /*false address translations due to the TLB if we didn't invalidate it.*/ /**/ xorl%eax, %eax movl%eax, %cr3/* Invalidate TLB*/ /* Invalidating the cache here seems to be a bad idea on * modern processors. Don't. * If we are hyperthreaded or we have multiple cores it is bad, * for SMP startup. On Opterons it causes a 5 second delay. * Invalidating the cache was pure paranoia in any event. * If you cpu needs it you can write a cpu dependent version of * entry16.inc. */ /* Note: gas handles memory addresses in 16 bit code very poorly. * In particular it doesn't appear to have a directive allowing you * associate a section or even an absolute offset with a segment register. * * This means that anything except cs:ip relative offsets are * a real pain in 16 bit mode. And explains why it is almost * imposible to get gas to do lgdt correctly. * * One way to work around this is to have the linker do the * math instead of the assembler. This solves the very * pratical problem of being able to write code that can * be relocated. * * An lgdt call before we have memory enabled cannot be * position independent, as we cannot execute a call * instruction to get our current instruction pointer. * So while this code is relocateable it isn't arbitrarily * relocatable. * * The criteria for relocation have been relaxed to their * utmost, so that we can use the same code for both * our initial entry point and startup of the second cpu. * The code assumes when executing at _start that: * (((cs 0xfff) == 0) and (ip == _start 0x)) * or * ((cs == anything) and (ip == 0)). * * The restrictions in reset16.inc mean that _start initially * must be loaded at or above 0x or below 0x10. * * The linker scripts computs gdtptr16_offset by simply returning * the low 16 bits. This means that the intial segment used * when start is called must be 64K aligned. This should not * restrict the address as the ip address can be anything. */ movw%cs, %ax shlw$4, %ax movw$gdtptr16_offset, %bx subw%ax, %bx data32 lgdt %cs:(%bx) movl%cr0, %eax andl$0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ orl $0x6001, %eax /* CD, NW, PE = 1 */ movl%eax, %cr0 /* Restore BIST to %eax */ movl%ebp, %eax /* Now that we are in protected mode jump to a 32 bit code segment. */ data32 ljmp$ROM_CODE_SEG,
Re: [coreboot] Missing entry16.inc for vx800
bari wrote: Here are the two missing entry16 files for the vx800. -Bari Why's that needed? Does the default not work? -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Missing entry16.inc for vx800
Stefan Reinauer wrote: bari wrote: Here are the two missing entry16 files for the vx800. -Bari Why's that needed? Does the default not work? For some reason the mystery developer c/o OLPC Inc. added this: /* 2008-12-2 added this--*/ /*Open A20 */ /*inb $0x92, %al orb $0x2,%al outb %al, $0x92*/ /*;--; ;Disable NMI and PARITY; ;--; */ /*movb $0x8d,%al*/ /*; disable parity*/ /*outb %al, $0x70 movb$0xc,%al */ /*; disable NMI*/ /*outb %al, $0x61*/ /* 2008-12-2 added this-*/ -Bari -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Missing entry16.inc for vx800
Stefan Reinauer wrote: Why's that needed? Does the default not work? For some reason the mystery developer c/o OLPC Inc. added this: /* 2008-12-2 added this--*/ /*Open A20 */ /*inb $0x92, %al orb $0x2,%al outb %al, $0x92*/ /*;--; ;Disable NMI and PARITY; ;--; */ /*movb $0x8d,%al*/ /*; disable parity*/ /*outb %al, $0x70 movb$0xc,%al */ /*; disable NMI*/ /*outb %al, $0x61*/ /* 2008-12-2 added this-*/ I only see comments there. Is there any new code that gets compiled in? Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Coreboot and ICH8M chipsets
Hi, I have a laptop with the ICH8M chipset for intel core 2 duo microprocessors. It seems like it is not yet supported by coreboot: is there anything I can do to speed the support process? Here are some info about my system: Motherboard: Manufacturer: Intel Corporation Product Name: SANTA ROSA CRB chipsets: Manufacturer: Intel Corporation Product Name: Crestline ICH8M Chipset processor: Intel Core 2 Duo The lspci -tvnn command gives me the following: -[:00]-+-00.0 Intel Corporation Mobile PM965/GM965/GL960 Memory Controller Hub [8086:2a00] +-01.0-[:01]00.0 nVidia Corporation GeForce 8600M GS [10de:0425] +-1a.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 [8086:2834] +-1a.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 [8086:2835] +-1a.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 [8086:283a] +-1b.0 Intel Corporation 82801H (ICH8 Family) HD Audio Controller [8086:284b] +-1c.0-[:02-03]00.0 Atheros Communications Inc. AR242x 802.11abg Wireless PCI Express Adapter [168c:001c] +-1c.2-[:04-05]00.0 Realtek Semiconductor Co., Ltd. RTL8101E/RTL8102E PCI Express Fast Ethernet controller [10ec:8136] +-1c.3-[:06-07]-- +-1d.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 [8086:2830] +-1d.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 [8086:2831] +-1d.2 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 [8086:2832] +-1d.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 [8086:2836] +-1e.0-[:08]-- +-1f.0 Intel Corporation 82801HEM (ICH8M) LPC Interface Controller [8086:2815] +-1f.2 Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) SATA IDE Controller [8086:2828] \-1f.3 Intel Corporation 82801H (ICH8 Family) SMBus Controller [8086:283e] I don't know what I/O chip is on the mainboard, and superiotool -dV fails to find anything, and the result of flashrom -V is attached in a file. And thanks for your hard work! Lionel flashrom_results Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] mkelfImage patch
Hello attached patch fixes when kernel binary has more than four section with was leading to corrupting memory and mysterious crash few functions later on illegal size for section that came from overwritten memory. best regards Maciej -- Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161 POE/Perl user mkelfImage-dirtyfix.diff Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] mkelfImage patch
please check http://www.coreboot.org/pipermail/coreboot/2009-March/045887.html YH On Sat, Jun 27, 2009 at 12:11 PM, Maciej Pijanka maciej.pija...@gmail.comwrote: Hello attached patch fixes when kernel binary has more than four section with was leading to corrupting memory and mysterious crash few functions later on illegal size for section that came from overwritten memory. best regards Maciej -- Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161 POE/Perl user -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
