[coreboot] Boot from IDE..
Guys, How can I put the Linux kernel in the Compact Flash on IDE? Coreboot is in BIOS chip then calling the Linux Compact Flash on IDE, I see it on FILO but I still don't understand, since the tutorial is for Qemu only.. Any help/ info will be so usefull for me Thanks -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4385 - in trunk/coreboot-v2/src: cpu/amd cpu/amd/socket_AM2r2 northbridge/amd/amdfam10 northbridge/amd/amdmct/mct northbridge/amd/amdmct/wrappers
Author: zbao
Date: 2009-07-01 09:01:32 +0200 (Wed, 01 Jul 2009)
New Revision: 4385
Added:
trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/
trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb
trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/chip.h
trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/socket_AM2r2.c
Modified:
trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c
trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctardk4.c
trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c
Log:
Add AMD family 10 AM2r2 support.
Coreboot used to take SYSTEM_TYPE as a lable to tell what the socket is.
This patch replaces (some of, not all) CONFIG_SYSTEM_TYPE with
CONFIG_SOCKET_TYPE.
It also fix some compiling error in src/northbridge/amd/amdmct/mct/mctardk4.c
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Marc Jones marcj...@gmail.com
Added: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb
===
--- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb
(rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb2009-07-01
07:01:32 UTC (rev 4385)
@@ -0,0 +1,54 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+uses CONFIG_PCI_IO_CFG_EXT
+uses CONFIG_MMCONF_SUPPORT
+uses CONFIG_HT3_SUPPORT
+uses CONFIG_EXT_RT_TBL_SUPPORT
+uses CONFIG_EXT_CONF_SUPPORT
+uses CONFIG_DIMM_SUPPORT
+uses CONFIG_CPU_SOCKET_TYPE
+uses CONFIG_CBB
+uses CONFIG_CDB
+uses CONFIG_PCI_BUS_SEGN_BITS
+uses CONFIG_CAR_FAM10
+
+config chip.h
+
+default CONFIG_PCI_IO_CFG_EXT=1
+
+default CONFIG_HT3_SUPPORT=1
+default CONFIG_EXT_RT_TBL_SUPPORT=0
+default CONFIG_EXT_CONF_SUPPORT=0
+default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG
+default CONFIG_CPU_SOCKET_TYPE=0x11
+
+default CONFIG_CAR_FAM10=1
+
+if CONFIG_EXT_RT_TBL_SUPPORT
+ default CONFIG_CBB=0xff
+ default CONFIG_CDB=0
+end
+
+#default CONFIG_MMCONF_SUPPORT=1
+#default CONFIG_MMCONF_SUPPORT_DEFAULT=1
+
+object socket_AM2r2.o
+
+dir /cpu/amd/model_10xxx
Added: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/chip.h
===
--- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/chip.h
(rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/chip.h 2009-07-01 07:01:32 UTC
(rev 4385)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations cpu_amd_socket_AM2r2_ops;
+
+struct cpu_amd_socket_AM2r2_config {
+};
Added: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/socket_AM2r2.c
===
--- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/socket_AM2r2.c
(rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/socket_AM2r2.c 2009-07-01
07:01:32 UTC (rev 4385)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ *
Re: [coreboot] [PATCH]:AMD family 10 AM2r2 support
CONFIG_ is added. Committed, r4385. -Original Message- From: Marc Jones [mailto:marcj...@gmail.com] Sent: Tuesday, June 30, 2009 11:23 PM To: Bao, Zheng Cc: coreboot@coreboot.org Subject: Re: [coreboot] [PATCH]:AMD family 10 AM2r2 support On Mon, Jun 29, 2009 at 11:46 PM, Bao, Zhengzheng@amd.com wrote: Add AMD family 10 AM2r2 support. Coreboot used to take SYSTEM_TYPE as a label to tell what the socket is. The patch replaces (some of, not all) SYSTEM_TYPE with CPU_SOCKET_TYPE. Signed-off-by: Zheng Bao zheng@amd.com T +default CPU_SOCKET_TYPE=0x11 Please add an equate for the socket names. Acked-by: Marc Jones marcj3...@gmail.com -- http://marcjonesconsulting.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4385
Dear coreboot readers! This is the automatic build system of coreboot. The developer zbao checked in revision 4385 to the coreboot repository. This caused the following changes: Change Log: Add AMD family 10 AM2r2 support. Coreboot used to take SYSTEM_TYPE as a lable to tell what the socket is. This patch replaces (some of, not all) CONFIG_SYSTEM_TYPE with CONFIG_SOCKET_TYPE. It also fix some compiling error in src/northbridge/amd/amdmct/mct/mctardk4.c Signed-off-by: Zheng Bao zheng@amd.com Acked-by: Marc Jones marcj...@gmail.com Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4385device=sandpointx3_altimus_mpc7410vendor=motorolanum=2 Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4385device=epia-m700vendor=vianum=2 If something broke during this checkin please be a pain in zbao's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4386
Dear coreboot readers! This is the automatic build system of coreboot. The developer rminnich checked in revision 4386 to the coreboot repository. This caused the following changes: Change Log: Ron, Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2. Patch should work against r4381 (or later ?) This version now boots all of the way through to attempting to launch a payload (I'm trying FILO right now), where it falls over with exception 6 (invalid opcode) The coreboot_table issue seems to have been automagically resolved by the latest core files. It may still be that the reason for the payload not starting is down to some issue with the tables initialising, I'll look closer at that. Signed-off-by: Jon Harrison both...@blueyonder.co.uk Acked-by: Ronald G. Minnich rminn...@gmail.com Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4386device=sandpointx3_altimus_mpc7410vendor=motorolanum=2 Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4386device=epia-m700vendor=vianum=2 Configuration of via:epia-n is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4386device=epia-nvendor=vianum=1 If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4387 - trunk/coreboot-v2/src/mainboard/via/epia-m700
Author: stepan Date: 2009-07-01 14:22:26 +0200 (Wed, 01 Jul 2009) New Revision: 4387 Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb Log: the file was not really different, so use the default file (trivial, since it didn't build before, and it still doesn't) Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb === --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb 2009-07-01 10:57:25 UTC (rev 4386) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb 2009-07-01 12:22:26 UTC (rev 4387) @@ -57,7 +57,7 @@ end end end -mainboardinit cpu/via/16bit/entry16.inc +mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/via/16bit/entry16.lds mainboardinit northbridge/via/vx800/romstrap.inc -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4388 - trunk/coreboot-v2/util/abuild
Author: stepan
Date: 2009-07-01 14:26:11 +0200 (Wed, 01 Jul 2009)
New Revision: 4388
Modified:
trunk/coreboot-v2/util/abuild/abuild
Log:
let abuild autodetect the coreboot path a bit better. So in the top level of
coreboot you can now do:
$ util/abuild/abuild -t foo/bar
instead of
$ util/abuild/abuild -t foo/bar $PWD
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified: trunk/coreboot-v2/util/abuild/abuild
===
--- trunk/coreboot-v2/util/abuild/abuild2009-07-01 12:22:26 UTC (rev
4387)
+++ trunk/coreboot-v2/util/abuild/abuild2009-07-01 12:26:11 UTC (rev
4388)
@@ -603,9 +603,12 @@
# default options
target=
buildall=false
-LBROOT=$( cd ../..; pwd )
verbose=false
+test -f util/newconfig/config.g LBROOT=$( pwd )
+test -f ../util/newconfig/config.g LBROOT=$( cd ..; pwd )
+test $LBROOT = LBROOT=$( cd ../..; pwd )
+
# parse parameters.. try to find out whether we're running GNU getopt
getoptbrand=`getopt -V`
if [ ${getoptbrand:0:6} == getopt ]; then
--
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[coreboot] build service results for r4387
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 4387 to the coreboot repository. This caused the following changes: Change Log: the file was not really different, so use the default file (trivial, since it didn't build before, and it still doesn't) Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4387device=sandpointx3_altimus_mpc7410vendor=motorolanum=2 Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4387device=epia-m700vendor=vianum=2 Configuration of via:epia-n is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4387device=epia-nvendor=vianum=1 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4388
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 4388 to the coreboot repository. This caused the following changes: Change Log: let abuild autodetect the coreboot path a bit better. So in the top level of coreboot you can now do: $ util/abuild/abuild -t foo/bar instead of $ util/abuild/abuild -t foo/bar $PWD Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4388device=sandpointx3_altimus_mpc7410vendor=motorolanum=2 Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4388device=epia-m700vendor=vianum=2 Configuration of via:epia-n is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4388device=epia-nvendor=vianum=1 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4389 - in trunk/coreboot-v2/src: include/device mainboard/via/epia-n southbridge/via/vt8237r
Author: rminnich
Date: 2009-07-01 15:19:25 +0200 (Wed, 01 Jul 2009)
New Revision: 4389
Modified:
trunk/coreboot-v2/src/include/device/pci_ids.h
trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb
trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
Log:
I missed three files.
Signed-off-by: Jon Harrison both...@blueyonder.co.uk
Acked-by: Ronald G. Minnich rminn...@gmail.com
Modified: trunk/coreboot-v2/src/include/device/pci_ids.h
===
--- trunk/coreboot-v2/src/include/device/pci_ids.h 2009-07-01 12:26:11 UTC
(rev 4388)
+++ trunk/coreboot-v2/src/include/device/pci_ids.h 2009-07-01 13:19:25 UTC
(rev 4389)
@@ -1198,6 +1198,14 @@
#define PCI_DEVICE_ID_VIA_CN700_VLINK 0x7314
#define PCI_DEVICE_ID_VIA_CN700_BRIDGE 0xB198
#define PCI_DEVICE_ID_VIA_CN700_VGA0x3344
+#define PCI_DEVICE_ID_VIA_CN400_AGP0x0259
+#define PCI_DEVICE_ID_VIA_CN400_ERR0x1259
+#define PCI_DEVICE_ID_VIA_CN400_HOST 0x2259
+#define PCI_DEVICE_ID_VIA_CN400_MEMCTRL0x3259
+#define PCI_DEVICE_ID_VIA_CN400_PM 0x4259
+#define PCI_DEVICE_ID_VIA_CN400_VLINK 0x7259
+#define PCI_DEVICE_ID_VIA_CN400_BRIDGE 0xB198
+#define PCI_DEVICE_ID_VIA_CN400_VGA0x3118
#define PCI_VENDOR_ID_SIEMENS 0x110A
#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102
Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb
===
--- trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb 2009-07-01
12:26:11 UTC (rev 4388)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb 2009-07-01
13:19:25 UTC (rev 4389)
@@ -58,7 +58,7 @@
uses CONFIG_HAVE_ACPI_RESUME
uses CONFIG_CROSS_COMPILE
uses CC
-uses CONFIG_HOSTCC
+uses HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
@@ -108,7 +108,7 @@
default CONFIG_ROM_PAYLOAD = 1
default CONFIG_CROSS_COMPILE =
default CC = $(CROSS_COMPILE)gcc -m32 -fno-stack-protector
-default CONFIG_HOSTCC = gcc
+default HOSTCC = gcc
#default CONFIG_MAINBOARD = EPIA-N
##
Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
===
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-07-01
12:26:11 UTC (rev 4388)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-07-01
13:19:25 UTC (rev 4389)
@@ -91,7 +91,7 @@
/* All delivered to CPU0. */
ioapic_table[0].value_high = (lapicid()) (56 - 32);
- l = (unsigned long *)ioapic_base;
+ l = (u32 *)ioapic_base;
/* Set APIC to FSB message bus. */
l[0] = 0x3;
@@ -243,26 +243,56 @@
{
u8 enables;
+ printk_spew(Entering vt8237r_init.\n);
+
+#ifdef CONFIG_EPIA_VT8237R_INIT
+ printk_spew(vt8237r_init SATA LED.\n);
/*
+* TODO: Looks like stock BIOS can do this but causes a hang
* Enable SATA LED, disable special CPU Frequency Change -
* GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+* Setup to match EPIA default
+* PCS0# on Pin U1
*/
- pci_write_config8(dev, 0xe5, 0x9);
+ enables = pci_read_config8(dev, 0xe5);
+ enables |= 0x02;
+ pci_write_config8(dev, 0xe5, enables);
+
+ printk_spew(vt8237r_init PCI Req.\n);
+ /*
+* Enable Flash Write Access.
+* Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
+*/
+ enables = pci_read_config8(dev, 0xe4);
+ enables |= 0x2B;
+ pci_write_config8(dev, 0xe4, enables);
+#else
+ /*
+* Enable SATA LED, disable special CPU Frequency Change -
+* GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+*/
+ pci_write_config8(dev, 0xe5, 0x09);
+
/* REQ5 as PCI request input - should be together with INTE-INTH. */
pci_write_config8(dev, 0xe4, 0x4);
+#endif
+
+ printk_spew(vt8237r_init CPU Rst.\n);
/* Set bit 3 of 0x4f (use INIT# as CPU reset). */
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
+ printk_spew(vt8237r_init Read Pass Write Ctrl.\n);
/*
* Set Read Pass Write Control Enable
* (force A2 from APIC FSB to low).
*/
pci_write_config8(dev, 0x48, 0x8c);
+ printk_spew(vt8237r_init calling southbridge_init_common.\n);
southbridge_init_common(dev);
/* FIXME: Intel needs more bit set for C2/C3. */
@@ -272,6 +302,8 @@
* Will work for C3 and for FID/VID change.
*/
outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
+
+ printk_spew(Leaving vt8237r_init.\n);
}
static void vt8237s_init(struct device *dev)
--
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Re: [coreboot] C3/CN400 Support - coreboot_tables
Jon's support code is now in the upstream. Thanks Jon! ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Intel Eagle Height evaluation board support
On Tue, Jun 30, 2009 at 7:40 PM, Kevin O'Connorke...@koconnor.net wrote: I would think coreboot should always configure the legacy PCI bridge bits and CONSOLE_VGA should just control whether or not coreboot tries to write to the screen. (Or, if there is a reason to not configure the pci ranges, then make it a separate config item.) It probably needs to be a config item then. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Intel Eagle Height evaluation board support
Hi Myles, all Could you send me the corrected Config.lb now that you removed the disabled devices? Here it is. As I said the audio and modem devices are disabled early so they won't be present and won't be enumerated despite the function exists in the i3100. Anyway, no internal connectors are present on the board for audio or modem. Thomas Config.lb Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4389
Dear coreboot readers! This is the automatic build system of coreboot. The developer rminnich checked in revision 4389 to the coreboot repository. This caused the following changes: Change Log: I missed three files. Signed-off-by: Jon Harrison both...@blueyonder.co.uk Acked-by: Ronald G. Minnich rminn...@gmail.com Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4389device=sandpointx3_altimus_mpc7410vendor=motorolanum=2 Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4389device=epia-m700vendor=vianum=2 Configuration of via:epia-n is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4389device=epia-nvendor=vianum=1 If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Intel Eagle Height evaluation board support
Hi Myles, guys Could you send the copyright line for your work? You made several non-trivial additions. I'll add it to the files for you. Is it mandatory ? A coreboot copyright is fine to me. If you need one, we can put : Copyright (C) 2009 Thomas Jourdan thomas.jour...@gmail.com Regards, Thomas -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] R4389 Adds EPIA-N(L) C3/CN400 Support - Developer Notes
Dear Corebooters ! R4389 has added initial support for Via C3/CN400/VT8237R based EPIA boards. This should cover EPIA-N, EPIA-NL and also some of the low end EPIA-SP boards. The build has been tested on a Via EPIA-NL 8000 fitted with 1GB DDR400 SDRAM. Current notes for the build for anyone seeking to develop further are as follows:: 1/ You need the VGA BIOS from factory BIOS and BOCHS to support the VGA init, as described in the EPIA-M/II HOWTO. 2/ ACPI is completely untested 3/ At this point the build does not actually get through the payload launch stage (may be a coreboot tables issue) The spew level output is attached, for reference for what to expect if you're working with epia-n. I'm working now to get FILO launching and then get ACPI working. Thanks, Jon SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England Wales. Company no. 02426132 This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. coreboot-2.0.0-r4389-epia_n-fallback Wed Jul 1 15:00:51 BST 2009 starting... In auto.c:main() Enabling mainboard devices Enable F-ROM Shadow RAM Setup CPU Interface CN400 RAM init starting Setting Burst Length 8 Low Bond 40 High Bond 7a Setting DQS delay66 CN400 Init done doing early_mtrr Leaving auto.c:main() Uncompressing coreboot to RAM. src=fffe dst=4000 Uncompressing image to RAM. image length = 000158d4 Jumping to image. coreboot-2.0.0-r4389-epia_n-fallback Wed Jul 1 15:00:51 BST 2009 booting... Calibrating delay loop... end 9fe7ea38, start 2c00e16c 32-bit delta 1854 calibrate_tsc 32-bit result is 1854 clocks_per_usec: 1854 Enumerating buses... Show all devs...Before Phase 3. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: : enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 1, 0 resources PCI: 00:00.3: enabled 1, 0 resources PCI: 00:00.4: enabled 1, 0 resources PCI: 00:00.7: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:0f.1: enabled 1, 0 resources PCI: 00:10.0: enabled 1, 0 resources PCI: 00:10.1: enabled 1, 0 resources PCI: 00:10.2: enabled 1, 0 resources PCI: 00:10.3: enabled 1, 0 resources PCI: 00:10.4: enabled 1, 0 resources PCI: 00:11.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 3 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 1 resources PNP: 002e.8: enabled 0, 1 resources PNP: 002e.9: enabled 0, 1 resources PNP: 002e.a: enabled 0, 1 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:11.5: enabled 0, 0 resources PCI: 00:12.0: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: : enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 1, 0 resources PCI: 00:00.3: enabled 1, 0 resources PCI: 00:00.4: enabled 1, 0 resources PCI: 00:00.7: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:0f.1: enabled 1, 0 resources PCI: 00:10.0: enabled 1, 0 resources PCI: 00:10.1: enabled 1, 0 resources PCI: 00:10.2: enabled 1, 0 resources PCI: 00:10.3: enabled 1, 0 resources PCI: 00:10.4: enabled 1, 0 resources PCI: 00:11.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 3 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 1 resources PNP: 002e.8: enabled 0, 1 resources PNP: 002e.9: enabled 0, 1 resources PNP: 002e.a: enabled 0, 1 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:11.5: enabled 0, 0 resources PCI: 00:12.0: enabled 1, 0 resources scan_static_bus for Root Device In cn400 enable_dev for device APIC_CLUSTER: 0. APIC_CLUSTER: 0 enabled In cn400 enable_dev for device PCI_DOMAIN: . Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: enabled PCI_DOMAIN: scanning... Entering cn400 pci_domain_scan_bus. PCI: pci_scan_bus for bus 00 In cn400 enable_dev for device PCI: 00:00.0. PCI: 00:00.0 [1106/0259] ops PCI: 00:00.0 [1106/0259] enabled In cn400 enable_dev for device PCI: 00:00.1. PCI: 00:00.1
[coreboot] [v2] r4390 - trunk/coreboot-v2/targets/via/epia-n
Author: myles Date: 2009-07-01 17:08:19 +0200 (Wed, 01 Jul 2009) New Revision: 4390 Modified: trunk/coreboot-v2/targets/via/epia-n/Config-abuild.lb Log: Fix abuild for via/epia-n. Trivial. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Modified: trunk/coreboot-v2/targets/via/epia-n/Config-abuild.lb === --- trunk/coreboot-v2/targets/via/epia-n/Config-abuild.lb 2009-07-01 13:19:25 UTC (rev 4389) +++ trunk/coreboot-v2/targets/via/epia-n/Config-abuild.lb 2009-07-01 15:08:19 UTC (rev 4390) @@ -5,7 +5,7 @@ option CC=CROSSCC option CONFIG_CROSS_COMPILE=CROSS_PREFIX -option CONFIG_HOSTCC=CROSS_HOSTCC +option HOSTCC=CROSS_HOSTCC __COMPRESSION__ __LOGLEVEL__ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4390
Dear coreboot readers! This is the automatic build system of coreboot. The developer myles checked in revision 4390 to the coreboot repository. This caused the following changes: Change Log: Fix abuild for via/epia-n. Trivial. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4390device=sandpointx3_altimus_mpc7410vendor=motorolanum=2 Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4390device=epia-m700vendor=vianum=2 Configuration of via:epia-n has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4391 - trunk/coreboot-v2/src/cpu/intel/model_6fx
Author: myles Date: 2009-07-01 18:34:03 +0200 (Wed, 01 Jul 2009) New Revision: 4391 Modified: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c Log: Fix typo and only output post code if the work was done. Thanks to Thomas Jourdan thomas.jour...@gmail.com for reporting it. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Modified: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c === --- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c 2009-07-01 15:08:19 UTC (rev 4390) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c 2009-07-01 16:34:03 UTC (rev 4391) @@ -50,9 +50,9 @@ wrmsr\n movl $MTRRphysMask_MSR(1), %ecx\n wrmsr\n -#endif movb $0x33, %al\noutb %al, $0x80\n +#endif #ifdef CLEAR_FIRST_1M_RAM movb $0x34, %al\noutb %al, $0x80\n /* Enable Write Combining and Speculative Reads for the first 1MB */ @@ -120,7 +120,7 @@ movb $0x3b, %al\noutb %al, $0x80\n /* Enable prefetchers */ - movl $0x01a0, %eax\n + movl $0x01a0, %ecx\n rdmsr\n andl $~((1 9) | (1 19)), %eax\n andl $~((1 5) | (1 7)), %edx\n -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Bug in cache_as_ram.inc and cache_as_ram_post.c
On Fri, Nov 28, 2008 at 2:16 PM, Thomas Jourdan tjour...@neuf.fr wrote: Hi guys I don't know how usefull is it but there is a bug in cache_as_ram.inc and cache_as_ram_post.c for the 6fx intel processors. The code disable / enable the prefetcher in IA32_MISC_ENABLES MSR register. Rev 4391. Sorry it took so long. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4391
Dear coreboot readers! This is the automatic build system of coreboot. The developer myles checked in revision 4391 to the coreboot repository. This caused the following changes: Change Log: Fix typo and only output post code if the work was done. Thanks to Thomas Jourdan thomas.jour...@gmail.com for reporting it. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4391device=sandpointx3_altimus_mpc7410vendor=motorolanum=2 Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4391device=epia-m700vendor=vianum=2 If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4392
Dear coreboot readers! This is the automatic build system of coreboot. The developer myles checked in revision 4392 to the coreboot repository. This caused the following changes: Change Log: Add support for the Intel Eagle Heights development board. Signed-off-by: Thomas Jourdan thomas.jour...@gmail.com Acked-by: Myles Watson myle...@gmail.com Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4392device=sandpointx3_altimus_mpc7410vendor=motorolanum=2 Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4392device=epia-m700vendor=vianum=2 If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] convert h8dmr to CBFS
The patch comment says it all... Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator Convert Supermicro H8DMR to CBFS. Also clean up some whitespace in targets/supermicro/h8dmr/Config.lb and Config-abuild.lb. Importantly, this also sets default CONFIG_AP_CODE_IN_CAR=0 in src/mainboard/supermicro/h8dmr/Options.lb which is required to make this box boot since the changes that went in in r4315. Build tested with abuild, boot tested on physical hardware. Signed-off-by: Ward Vandewege w...@gnu.org Index: src/mainboard/supermicro/h8dmr/Config.lb === --- src/mainboard/supermicro/h8dmr/Config.lb (revision 4392) +++ src/mainboard/supermicro/h8dmr/Config.lb (working copy) @@ -58,7 +58,6 @@ depends $(CONFIG_MAINBOARD)/apc_auto.c option_table.h action $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@ end -ldscript /arch/i386/init/ldscript_apc.lb end end Index: src/mainboard/supermicro/h8dmr/Options.lb === --- src/mainboard/supermicro/h8dmr/Options.lb (revision 4392) +++ src/mainboard/supermicro/h8dmr/Options.lb (working copy) @@ -126,13 +126,9 @@ default CONFIG_ROM_SIZE=0x10 ## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x4 - -#FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -234,7 +230,7 @@ default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 -default CONFIG_AP_CODE_IN_CAR=1 +default CONFIG_AP_CODE_IN_CAR=0 default CONFIG_MEM_TRAIN_SEQ=1 default CONFIG_WAIT_BEFORE_CPUS_INIT=1 @@ -256,8 +252,9 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 0xf000 + ## ## Use a small 8K stack ## @@ -352,5 +349,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Index: targets/supermicro/h8dmr/Config-abuild.lb === --- targets/supermicro/h8dmr/Config-abuild.lb (revision 4392) +++ targets/supermicro/h8dmr/Config-abuild.lb (working copy) @@ -11,27 +11,25 @@ __LOGLEVEL__ romimage normal -option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x2 option COREBOOT_EXTRA_VERSION=.0-normal payload __PAYLOAD__ end romimage fallback -option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x2 option COREBOOT_EXTRA_VERSION=.0-fallback payload __PAYLOAD__ end romimage failover -option CONFIG_USE_FAILOVER_IMAGE=1 -option CONFIG_USE_FALLBACK_IMAGE=0 -option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE -option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -option COREBOOT_EXTRA_VERSION=.0-failover + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE + option COREBOOT_EXTRA_VERSION=.0-failover end buildrom ./coreboot.rom CONFIG_ROM_SIZE normal fallback failover Index: targets/supermicro/h8dmr/Config.lb === --- targets/supermicro/h8dmr/Config.lb (revision 4392) +++ targets/supermicro/h8dmr/Config.lb (working copy) @@ -23,44 +23,25 @@ mainboard supermicro/h8dmr romimage normal -# 48K for SCSI FW -#option CONFIG_ROM_SIZE = 475136 -# 48K for SCSI FW and 48K for ATI ROM -# option CONFIG_ROM_SIZE = 425984 -# 64K for Etherboot -#option CONFIG_ROM_SIZE = 458752 -# 44k for atixx.rom -#option CONFIG_ROM_SIZE = 479232 -option CONFIG_USE_FAILOVER_IMAGE=0 - option CONFIG_USE_FALLBACK_IMAGE=0 -# option CONFIG_ROM_IMAGE_SIZE=0x13800 -# option CONFIG_ROM_IMAGE_SIZE=0x18800 - option CONFIG_ROM_IMAGE_SIZE=0x2 -# option CONFIG_ROM_IMAGE_SIZE=0x15800 - option CONFIG_XIP_ROM_SIZE=0x4 - option COREBOOT_EXTRA_VERSION=$(shell cat ../../VERSION)_Normal - payload ../payload.elf + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option COREBOOT_EXTRA_VERSION=$(shell cat ../../VERSION)_Normal + payload ../payload.elf end romimage fallback - option CONFIG_USE_FAILOVER_IMAGE=0 - option CONFIG_USE_FALLBACK_IMAGE=1 -# option CONFIG_ROM_IMAGE_SIZE=0x13800 -# option
Re: [coreboot] [PATCH] convert h8dmr to CBFS
Signed-off-by: Ward Vandewege w...@gnu.org If you put default CONFIG_USE_FAILOVER_IMAGE=0 default CONFIG_USE_FALLBACK_IMAGE=0 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE In Options.lb it would clean up your Config.lb files a little more. Acked-by: Myles Watson myle...@gmail.com Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Copyright [was: Intel Eagle Height evaluation board support]
Hello Thomas, Thanks a lot for your contributions to coreboot! Thomas JOURDAN wrote: Is it mandatory ? Yes. A coreboot copyright is fine to me. Please note that there is no coreboot legal entity. Unfortunately the name of Stefan Reinauer's company, coresystems GmbH, is quite similar to the name of this project and the two could easily be confused - but please keep in mind that coresystems GmbH is only one part of the greater coreboot community. While Stefan and Patrick do some amazing work with coreboot, I am sure that it is not the intention of coresystems GmbH to own copyright for all coreboot code. Copyright (C) 2009 Thomas Jourdan thomas.jour...@gmail.com Great! Thanks. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot VGA init vs. writes [was: Intel Eagle Height evaluation board support]
Myles Watson wrote: If Coreboot never writes to the console, that fixes it too. I think that was Stefan's preferred solution. I like that too! Where does coreboot write to VGA now? I think he's right that most of the time the VGA console is useless for debugging. All the tricky things happen before that's available. Agree. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Info for EPIA m700 and EPIA n700
Hi all Here is some info on two Via EPIA boards, you can find them here: http://irc.walkyrie.se/coreboot/EPIA_m700/ http://irc.walkyrie.se/coreboot/EPIA_n700/ and some pictures of the boards, which I release to public domain: http://irc.walkyrie.se/coreboot/pictures/ Cheers Jakob. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot VGA init vs. writes [was: Intel Eagle Height evaluation board support]
On Wed, Jul 1, 2009 at 4:07 PM, Peter Stuge pe...@stuge.se wrote: Myles Watson wrote: If Coreboot never writes to the console, that fixes it too. I think that was Stefan's preferred solution. I like that too! Where does coreboot write to VGA now? from printk as soon as it thinks the console is initialized when CONSOLE_VGA is set. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Boot from IDE..
Hi Rick, Rick Ant wrote: How can I put the Linux kernel in the Compact Flash on IDE? Putting it there is easy on another system with a CF reader. To boot it in a system which uses coreboot, you must use a payload which has drivers for IDE and the filesystem which is used on the CF card. FILO, Linux and maybe GRUB 2 should be good choices. Coreboot is in BIOS chip then calling the Linux Compact Flash on IDE, No! coreboot does not call anything on IDE. coreboot starts the payload, FILO, and then coreboot is out of the picture. FILO has drivers for IDE and several filesystems, and can be used to load the Linux kernel. I see it on FILO What exactly do you see on FILO? Please be careful to include more detail when you ask for help. It is impossible to help you when you are so brief. but I still don't understand, since the tutorial is for Qemu only.. That does not matter in this case. Qemu also has IDE devices. If FILO does not detect your CF card, one suggestion you can try is to build FILO with more debugging. Enable the relevant debug options for your configuration. It is also helpful if you send debugging output. If you do not send that output, you are MUCH less likely to get any response at all, as you may have noticed, simply because it is impossible to help you without more information than you provide. Thanks //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]:AMD family 10 AM2r2 support
Bao, Zheng wrote: +default CPU_SOCKET_TYPE=0x11 Please add an equate for the socket names. CONFIG_ is added. I think what Marc meant is to add a #define with a sensible name, for each socket type, instead of using 0x11 directly. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] C3/CN400 Support - coreboot_tables
Harrison, Jon (SELEX GALILEO, UK) wrote: This version now boots all of the way through to attempting to launch a payload (I'm trying FILO right now), where it falls over with exception 6 (invalid opcode) Please start with memtest86 or memtest86+ as payload, and let it run a few days. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Patches long forgotten
Bao, Zheng wrote: Can you tell me which is the patch or send it to me? This is why we need patchwork. Patrick, do you think you'll have a chance to set it up or should I have a go? //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Patches long forgotten
On Thu, 2 Jul 2009 01:05:20 +0200, Peter Stuge pe...@stuge.se wrote: Bao, Zheng wrote: Can you tell me which is the patch or send it to me? This is why we need patchwork. Patrick, do you think you'll have a chance to set it up or should I have a go? YES, much agreed! -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Info for EPIA m700 and EPIA n700
Hi Jakob, no offense intended, but getpir recently got an update which caused it to print incorrect file headers. The irq_table.c snippet below looks like you used that getpir version and followed the instructions, so I won't blame you. I didn't yet have time (and energy) to revert that change to getpir. If you got irq_table.c by running getpir, it is most likely not under the GPL and also not your copyright. It might be possible that the results of getpir can be classified as non-copyrightable data, but even then applying the GPL to data someone else created feels wrong. For now, I have to ask you to rerun getpir from revision 4295 which has somewhat different output without bogus license information. Thanks. If you created irq_table.c from scratch or based your own routing layout on getpir results, please accept my apologies. Regards, Carl-Daniel On 02.07.2009 00:50, Jakob Bornecrantz wrote: /* * This file is part of the coreboot project. * * Copyright (C) 2009 Jakob Bornecrantz wallbra...@gmail.com * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. [...] */ #ifdef GETPIR /* TODO: Drop this when copying to coreboot. */ #include pirq_routing.h /* TODO: Drop this when copying to coreboot. */ #else /* TODO: Drop this when copying to coreboot. */ #include arch/pirq_routing.h #endif/* TODO: Drop this when copying to coreboot. */ -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Info for EPIA m700 and EPIA n700
On Thu, Jul 2, 2009 at 1:22 AM, Carl-Daniel Hailfingerc-d.hailfinger.devel.2...@gmx.net wrote: Hi Jakob, no offense intended, but getpir recently got an update which caused it to print incorrect file headers. The irq_table.c snippet below looks like you used that getpir version and followed the instructions, so I won't blame you. I didn't yet have time (and energy) to revert that change to getpir. If you got irq_table.c by running getpir, it is most likely not under the GPL and also not your copyright. It might be possible that the results of getpir can be classified as non-copyrightable data, but even then applying the GPL to data someone else created feels wrong. For now, I have to ask you to rerun getpir from revision 4295 which has somewhat different output without bogus license information. Thanks. Yes it was a broken version I will re run. If you created irq_table.c from scratch or based your own routing layout on getpir results, please accept my apologies. No i did not write them myself, I assumed it was okay to add it since mptable adds a copyright automatically, I'm sorry. Cheers Jakob. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Info for EPIA m700 and EPIA n700
On Thu, Jul 2, 2009 at 1:22 AM, Carl-Daniel
Hailfingerc-d.hailfinger.devel.2...@gmx.net wrote:
Hi Jakob,
no offense intended, but getpir recently got an update which caused it
to print incorrect file headers. The irq_table.c snippet below looks
like you used that getpir version and followed the instructions, so I
won't blame you.
I didn't yet have time (and energy) to revert that change to getpir.
If you got irq_table.c by running getpir, it is most likely not under
the GPL and also not your copyright. It might be possible that the
results of getpir can be classified as non-copyrightable data, but even
then applying the GPL to data someone else created feels wrong. For now,
I have to ask you to rerun getpir from revision 4295 which has somewhat
different output without bogus license information. Thanks.
Here are the new results from getpir.
Cheers Jakob.
/* This file was generated by getpir.c, do not modify!
* (but if you do, please run checkpir on it to verify)
*
* Contains the IRQ Routing Table dumped directly from your
* memory, which BIOS sets up.
*
* Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
*/
#ifdef GETPIR
#include pirq_routing.h
#else
#include arch/pirq_routing.h
#endif
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION,/* u16 version */
32+16*13, /* There can be total 13 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x113)|0x0, /* Where the interrupt router lies (dev) */
0xca0, /* IRQs devoted exclusively to PCI usage */
0x1106, /* Vendor */
0x596, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xdb, /* u8 checksum. This has to be set to some
value that would give 0 after the sum of all
bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x023)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x1, 0x0},
{0x00,(0x033)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x2, 0x0},
{0x00,(0x033)|0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x3, 0x0},
{0x04,(0x043)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}}, 0x4, 0x0},
{0x04,(0x0e3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x5, 0x0},
{0x00,(0x113)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
{0x00,(0x0f3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
{0x00,(0x013)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
{0x00,(0x103)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
{0x00,(0x023)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0},
{0x00,(0x033)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0},
{0x00,(0x033)|0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0},
{0x00,(0x143)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
}
/* This file was generated by getpir.c, do not modify!
* (but if you do, please run checkpir on it to verify)
*
* Contains the IRQ Routing Table dumped directly from your
* memory, which BIOS sets up.
*
* Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
*/
#ifdef GETPIR
#include pirq_routing.h
#else
#include arch/pirq_routing.h
#endif
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION,/* u16 version */
32+16*13, /* There can be total 13 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x113)|0x0, /* Where the interrupt router lies (dev) */
0xce0, /* IRQs devoted exclusively to PCI usage */
0x1106, /* Vendor */
0x596, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x23, /* u8 checksum. This has to be set to some
value that would give 0 after the sum of all
bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x023)|0x0, {{0x09, 0xcef8}, {0x09, 0xcef8}, {0x09, 0xcef8}, {0x09, 0xcef8}}, 0x1, 0x0},
{0x00,(0x033)|0x0, {{0x09, 0xcef8}, {0x09, 0xcef8}, {0x09, 0xcef8}, {0x09, 0xcef8}}, 0x2, 0x0},
{0x00,(0x033)|0x1, {{0x09, 0xcef8}, {0x09, 0xcef8}, {0x09, 0xcef8}, {0x09, 0xcef8}}, 0x3, 0x0},
{0x04,(0x033)|0x0, {{0x03, 0xcef8}, {0x05, 0xcef8}, {0x01, 0xcef8}, {0x02, 0xcef8}}, 0x4, 0x0},
{0x04,(0x0e3)|0x0, {{0x05, 0xcef8}, {0x03, 0xcef8}, {0x02, 0xcef8}, {0x01, 0xcef8}}, 0x5, 0x0},
Re: [coreboot] libpayload question
Warren Turkal wrote: Actually, I just found coreinfo. Can it be launched by grub? Don't know. Try it. Etherboot and FILO can both start payloads as were they kernels. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [flashrom] [PATCH] external serial flasher protocol support
Urja Rannikko wrote: You may want to add the following commands for handling of CE#, OE#, WE#. .. GPIO .. one would need to define the GPIO's too. Keep them out of the protocol. These signals must not be messed with at this high level, they are all in the programmer domain. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
