[coreboot] [PATCH] Fix out{b,l} buglets
Apparently I'm not the only one who forgets which way the outb and outl
arguments go.
Signed-off-by: Ed Swierk eswi...@aristanetworks.com
---
Index: coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
===
--- coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
(revision 4415)
+++ coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
(working copy)
@@ -38,7 +38,7 @@
byte |= ( 1 7); // Can not mask NMI from PCI-E and NMI_NOW
}
if( byte != byte_old) {
- outb(0x70, byte);
+ outb(byte, 0x70);
}
Index: coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
===
--- coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c(revision 4415)
+++ coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c(working copy)
@@ -245,7 +245,7 @@
byte |= (1 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
}
if (byte != byte_old)
- outb(0x70, byte);
+ outb(byte, 0x70);
/* Initialize the real time clock (RTC). */
rtc_init(0);
Index: coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
===
--- coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c(revision 4415)
+++ coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c(working copy)
@@ -230,7 +230,7 @@
byte |= ( 1 7); // Can not mask NMI from PCI-E and NMI_NOW
}
if( byte != byte_old) {
- outb(0x70, byte);
+ outb(byte, 0x70);
}
/* Initialize the real time clock */
Index: coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c
===
--- coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c (revision 4415)
+++ coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c (working copy)
@@ -220,7 +220,7 @@
byte |= ( 1 7); // Can not mask NMI from PCI-E and NMI_NOW
}
if( byte != byte_old) {
-outb(0x70, byte);
+outb(byte, 0x70);
}
/* Initialize the real time clock */
Index: coreboot-v2/src/cpu/amd/sc520/raminit.c
===
--- coreboot-v2/src/cpu/amd/sc520/raminit.c (revision 4415)
+++ coreboot-v2/src/cpu/amd/sc520/raminit.c (working copy)
@@ -183,16 +183,16 @@
/* Stepan says: This needs to go to the msm586seg code */
/* enumerate the PCI. Mainly set the interrupt bits on the PCnetFast. */
- outl(0xcf8, 0x08000683c);
- outl(0xcfc, 0xc); /* set the interrupt line */
+ outl(0x08000683c, 0xcf8);
+ outl(0xc, 0xcfc); /* set the interrupt line */
/* Set the SC520 PCI host bridge to target mode to
* allow external bus mastering events
*/
/* index the status command register on device 0*/
- outl(0x0cf8,0x08004);
- outl(0xcfc, 0x2); /*set the memory access enable bit*/
+ outl(0x08004, 0x0cf8);
+ outl(0x2, 0xcfc); /*set the memory access enable bit*/
OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */
}
--
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Re: [coreboot] Dell latitude c610
Le vendredi 26 juin 2009 21:10:16, Uwe Hermann a écrit : Hi, On Fri, Jun 26, 2009 at 12:33:14PM +0200, CybFr wrote: I'd like to re-open a tread from Michal Janke about supporting Dell latitude C610 and its SMSC LPC47N252 SuperIO. - I've found the closest chip from SMSC was FDC37N972, supported by superiotool so I added corresponding entries in smsc.c. - for FDC, UARTS, KBD, RTC, everything seems quite common so I added it in /superio/smsc/smsssuperio/superio.c. (the big difference betweenn supported smsc chips an LPC47N252 is the EC-8051 core... ) What could be the next step ? The next step would probably be to find out where the EC code lives in the flash ROM chip, make a coreboot.rom which leaves that area empty and then 'dd' the EC blob over the empty area. Flash that, attach a POST card and/or null-modem cable and see what happens... Waiting for chips, sockets and a replacement mothercard (just in case), I try to find the EC code both from a dump of th flash rom and from the Dell bios file. But from the LPC47N252 datasheet I understand that it is supposed to execute its firmware directly from its own flash (which doesn't exist on FDC37N958FR). If I'm right, the bad point would be that I have no chance to get a blob from FWH but the good point could be that we can forget about EC code (unless we want to update it). Am I right ??? PS: Uwe, I don't know if you received my mail with pictures (sent last monday) BTW I put them there http://www.miradou.com/spip/spip.php?article14 -- CybFr -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [Patch] superiotool: Add IT8703F support.
On Thu, Jul 09, 2009 at 06:36:59PM +0200, Luc Verhaegen wrote:
Superiotool: Add IT8703F support.
Kudos to ITE for quickly providing information.
Signed-off-by: Luc Verhaegen l...@skynet.be
Looks good, but see below for minor consistency fixes.
Index: ite.c
===
--- ite.c (revision 4407)
+++ ite.c (working copy)
@@ -66,6 +66,44 @@
{EOT}}},
{0x8681, IT8671F/IT8687R, {
{EOT}}},
+ {0x8701, IT8703F, {
+ {NOLDN, NULL,
+ {0x20,0x21,0x23,0x24,0x26,0x29,0x2A,0x2B,EOT},
+ {0x87,0x00,0x00,0x80,0x00,0x00,0x7C,0xC0,EOT}},
^
Indent this part by one TAB also please (and wrap lines at 80 chars if
needed) to match the rest of superiotool style.
+ {0x0, Floppy Disk Controller,
Also, Floppy disk controller (or even just Floppy), i.e., only first
word capitalized, to match the conventions in rest of superiotool. The
same applies to the other LDNs (Parallel port etc). Consumer IR is
fine as IR is an abbreviation.
Other than that:
Acked-by: Uwe Hermann u...@hermann-uwe.de
Uwe.
--
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Re: [coreboot] Dell latitude c610
CybFr wrote: Waiting for chips, sockets and a replacement mothercard Note that SST 49LF004 is not a parallel flash chip, but rather an FWH type chip. What replacement chip did you order? If same part number it's of course compatible. :) //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dell latitude c610
On Fri, Jul 10, 2009 at 10:30:40AM +0200, CybFr wrote: PS: Uwe, I don't know if you received my mail with pictures (sent last monday) BTW I put them there http://www.miradou.com/spip/spip.php?article14 Yep, got the mail, will upload stuff today, was a bit busy until now. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dell latitude c610
PS: Uwe, I don't know if you received my mail with pictures (sent last monday) BTW I put them there http://www.miradou.com/spip/spip.php?article14 Nice pics :-) Right now the i830 is only setup for onboard graphics not AGP. Let me know when your ready and I would be glad to help you get it working. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] m57sli, seabios and gpxe - kernel booting issues (BUG: INT 14 etc)
On Tue, Jul 07, 2009 at 10:51:56PM -0400, Ward Vandewege wrote: On Wed, Jul 08, 2009 at 12:53:02AM +0200, Peter Stuge wrote: Ward Vandewege wrote: I'm trying to do a GPXE boot from seabios with coreboot on m57sli, .. With 2.6.30, I get absolutely nothing, the kernel just hangs without output. That's with the multi-segment patched mkelfImage or with the ordinary older mkelfImage. Are you sure mkelfImage is good also for GPXE? Oh, and did you try sending the plain vmlinux ELF? Hmmm, good question. I just assumed - these machines currently run an old version of coreboot with etherboot, which takes mkelfImage generated files. Will test and report back... OK. For the record, it works perfectly if you use wraplinux. I guess there is a bug somewhere in mkelfImage... http://git.etherboot.org/?p=wraplinux.git;a=summary Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot on Asus G1 ... Possible ?
Ivan Barrera A. escribió: Hi ! Ive just joined the mailing list, to see if it is possible to get an Asus G1 (laptop) use coreboot. I recently killed my bios doing some experiments, so i desoldered the chip, and put a nice socket. (it is a PLCC32). Also i have the equipment needed to program this chip, so no worries there. Details : - Laptop : Asus G1 , first revisions. IMPORTANT NOTE: Video card is a Geforce Go 7700 512MB, and video bios is integrated as a module in bios rom (amibios) - Attached lspci outpu - No super io chip (it seems) - PLCC32 SST49LF004B (49LF004B-33-4C-NH Rev CA, according to specs it is lpc/fwh) - Host bridge: Intel Corporation Mobile 945GM/PM/GMS - South Bridge : ICH7 Family - Bios : http://ivn.cl/software/asus_g1.rom (read with flasrom) No go for this one :( Flashed coreboot v2 (kontron), added video rom, adjusted for 512KB. flashrom didnt work, so i used my programmer with the corresponding FWH/LPC+ adaptor. System turned on. Blank screen. Wasnt able to measure voltages on the chip socket, as my voltimeter battery died.. so it will be for another time. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] m57sli, seabios and gpxe - kernel booting issues (BUG: INT 14 etc)
Ward Vandewege wrote: Are you sure mkelfImage is good also for GPXE? Oh, and did you try sending the plain vmlinux ELF? OK. For the record, it works perfectly if you use wraplinux. I guess there is a bug somewhere in mkelfImage... http://git.etherboot.org/?p=wraplinux.git;a=summary Just a note that wraplinux requires SeaBIOS. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [patch]:new dual core check function in sb600.
Acked-by: Ronald G. Minnich rminn...@gmail.com It still looks good :-) -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dell latitude c610
Le vendredi 10 juillet 2009 15:21:50, Peter Stuge a écrit : CybFr wrote: Waiting for chips, sockets and a replacement mothercard Note that SST 49LF004 is not a parallel flash chip, but rather an FWH type chip. You're right, it has a FWH interface for in-system operations and it has parallal programming capability. What replacement chip did you order? If same part number it's of course compatible. :) The only one I found is an AM29F040 given as read compatible (by my local reseller) but looking at datasheets, I'm very sceptic... Does anybody know a source fot SST49LF004A ? -- FR -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Fix out{b,l} buglets
On Fri, Jul 10, 2009 at 6:17 AM, Peter Stugepe...@stuge.se wrote: Acked-by: Peter Stuge pe...@stuge.se Thanks, committed in r4422. --Ed -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Televideo TC7020
I have recently come into possession of a Televideo TC7020 thin client runnning Windows CE. I have read as much as I could about altering this to boot to Linux, but there are a few things that I am still not certain about. I got this item from my work (an electronics recycling company) and it has an administrator password set on it that prevents me from accessing anything installed on it currently. Here is what I am planning on doing so far, please let me know if I am way off base. 1) Build File and Coreboot on another linux machine that uses the same BIOS chip. 2) Use flashrom to hotflash the BIOS chip from the TC7020 in the same linux machine 3) Put the BIOS chip back in the TC7020 and attempt to make it boot linux from a laptop HDD. Any tips/suggestions/constructive criticism would be extremely helpful. Thanks in Advance -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Televideo TC7020
On Fri, Jul 10, 2009 at 1:23 PM, Ryan jesusbass...@gmail.com wrote: I have recently come into possession of a Televideo TC7020 thin client runnning Windows CE. I have read as much as I could about altering this to boot to Linux, but there are a few things that I am still not certain about. I got this item from my work (an electronics recycling company) and it has an administrator password set on it that prevents me from accessing anything installed on it currently. Here is what I am planning on doing so far, please let me know if I am way off base. 1) Build File and Coreboot on another linux machine that uses the same BIOS chip. 2) Use flashrom to hotflash the BIOS chip from the TC7020 in the same linux machine 3) Put the BIOS chip back in the TC7020 and attempt to make it boot linux from a laptop HDD. Sounds good. I'm assuming you've seen this page: http://www.coreboot.org/TeleVideo_TC7020 Good luck, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] flashrom: Tarball improvements
On 30.06.2009 14:53, Carl-Daniel Hailfinger wrote: Change tarball compression from gzip to bzip2. Set the user and group of all files to root for tar versions which support it. Add explanatory comments for supporting that feature with other tar versions. Use LC_ALL instead of LANG everywhere. Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net Thanks to Stefan for the Ack. Committed in r644. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dell latitude c610
On Fri, Jul 10, 2009 at 03:46:56PM +0200, Uwe Hermann wrote: On Fri, Jul 10, 2009 at 10:30:40AM +0200, CybFr wrote: PS: Uwe, I don't know if you received my mail with pictures (sent last monday) BTW I put them there http://www.miradou.com/spip/spip.php?article14 Yep, got the mail, will upload stuff today, was a bit busy until now. Done. http://www.coreboot.org/Dell_Latitude_C610 Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dell latitude c610
CybFr wrote: Waiting for chips, sockets and a replacement mothercard Note that SST 49LF004 is not a parallel flash chip, but rather an FWH type chip. You're right, it has a FWH interface for in-system operations and it has parallal programming capability. Yeah, the A/A thing. That's will rarely if ever work in-system though. What replacement chip did you order? If same part number it's of course compatible. :) The only one I found is an AM29F040 given as read compatible (by my local reseller) but looking at datasheets, I'm very sceptic... Sorry, that isn't compatible at all. Does anybody know a source fot SST49LF004A ? Am a little web challenged right now, but it should be possible to find that or a compatible chip. Look for any SST49LF00xx chip. 008B will work fine. You can also look for Winbond W39VxxxFA.. chips, or ST M50W-something which are dual LPC/FWH. I am pretty sure farnell.com has some compatible chip at a fair price. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [flashrom] [PATCH] external serial flasher protocol support
On Sun, Jun 28, 2009 at 18:49, Urja Rannikkourja...@gmail.com wrote:
Support for an external serial flasher protocol.
Supports RS-232, USB serial converters (untested) and TCP streams.
Signed-off-by: Urja Rannikko urja...@gmail.com
---
A small update - compiles without warnings on x86-64 now (printf of an
size_t changed to use %lu and cast the size_t to unsigned long). Also
made sure the serial port input doesnt mangle the CR/NL bytes.
Patch inlined:
Index: serprog.c
===
--- serprog.c (revision 643)
+++ serprog.c (working copy)
@@ -39,9 +39,747 @@
char *serprog_param = NULL;
-#define SERPROG_SUPPORT 0
+#define SERPROG_SUPPORT 1
+
#if SERPROG_SUPPORT == 1
+
+#define MSGHEADER serprog:
+
+#define S_ACK 0x06
+#define S_NAK 0x15
+#define S_CMD_NOP 0x00/* No operation
*/
+#define S_CMD_Q_IFACE 0x01/* Query interface version
*/
+#define S_CMD_Q_CMDMAP 0x02/* Query supported commands bitmap
*/
+#define S_CMD_Q_PGMNAME0x03/* Query programmer name
*/
+#define S_CMD_Q_SERBUF 0x04/* Query Serial Buffer Size
*/
+#define S_CMD_Q_BUSTYPE0x05/* Query supported bustypes
*/
+#define S_CMD_Q_CHIPSIZE 0x06/* Query supported chipsize (2^n
format)*/
+#define S_CMD_Q_OPBUF 0x07/* Query operation buffer size
*/
+#define S_CMD_Q_WRNMAXLEN 0x08/* Query opbuf-write-N maximum lenght
*/
+#define S_CMD_R_BYTE 0x09/* Read a single byte
*/
+#define S_CMD_R_NBYTES 0x0A/* Read n bytes
*/
+#define S_CMD_O_INIT 0x0B/* Initialize operation buffer
*/
+#define S_CMD_O_WRITEB 0x0C/* Write opbuf: Write byte with address
*/
+#define S_CMD_O_WRITEN 0x0D/* Write to opbuf: Write-N
*/
+#define S_CMD_O_DELAY 0x0E/* Write opbuf: udelay
*/
+#define S_CMD_O_EXEC 0x0F/* Execute operation buffer
*/
+#define S_CMD_SYNCNOP 0x10/* Special no-operation that returns
NAK+ACK*/
+#define S_CMD_Q_RDNMAXLEN 0x11/* Query read-n maximum length
*/
+#define S_CMD_S_BUSTYPE0x12/* Set used bustype(s).
*/
+
+static int sp_fd;
+
+static uint16_t sp_device_serbuf_size = 16;
+static uint16_t sp_device_opbuf_size = 300;
+/* Bitmap of supported commands */
+static uint8_t sp_cmdmap[32];
+
+/* sp_prev_was_write used to detect writes with continouous addresses
+ and combine them to write-n's */
+static int sp_prev_was_write = 0;
+/* sp_write_n_addr used as the starting addr of the currently
+ combined write-n operation */
+static uint32_t sp_write_n_addr;
+/* The maximum length of an write_n operation; 0 = write-n not supported */
+static uint32_t sp_max_write_n = 0;
+/* The maximum length of a read_n operation; 0 = 2^24 */
+static uint32_t sp_max_read_n = 0;
+
+/* A malloc'd buffer for combining the operation's data
+ and a counter that tells how much data is there. */
+static uint8_t *sp_write_n_buf;
+static uint32_t sp_write_n_bytes = 0;
+
+/* sp_streamed_* used for flow control checking */
+static int sp_streamed_transmit_ops = 0;
+static int sp_streamed_transmit_bytes = 0;
+
+/* sp_opbuf_usage used for counting the amount of
+ on-device operation buffer used */
+static int sp_opbuf_usage = 0;
+/* if true causes sp_docommand to automatically check
+ whether the command is supported before doing it */
+static int sp_check_avail_automatic = 0;
+
+static void sp_die(char *msg)
+{
+ perror(msg);
+ exit(1);
+}
+
+static int sp_opensocket(char *ip, unsigned int port)
+{
+ int flag = 1;
+ struct hostent *hostPtr = NULL;
+ struct sockaddr_in sp;
+ int sock;
+ printf_debug(MSGHEADER IP %s port %d\n, ip, port);
+ sock = socket(PF_INET, SOCK_STREAM, IPPROTO_TCP);
+ if (sock 0)
+ sp_die(Error: serprog cannot open socket);
+ hostPtr = gethostbyname(ip);
+ if (NULL == hostPtr) {
+ hostPtr = gethostbyaddr(ip, strlen(ip), AF_INET);
+ if (NULL == hostPtr)
+ sp_die(Error: cannot resolve);
+ }
+ memset(sp, 0, sizeof(sp));
+ sp.sin_family = AF_INET;
+ sp.sin_port = htons(port);
+ (void)memcpy(sp.sin_addr, hostPtr-h_addr, hostPtr-h_length);
+ if (connect(sock, (struct sockaddr *)sp, sizeof(sp)) 0) {
+ close(sock);
+ sp_die(Error: serprog cannot connect);
+ }
+ /* We are latency limited, and sometimes do write-write-read*
+* (write-n) - so enable TCP_NODELAY.
